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international rectifier ? 233 kansas street, el segundo, ca 90245 usa ! irmck203 application developer?s guide february 19, 2004 version 1.0 ir world headquarters: 233 kansas st., el segundo, california 90245 tel: (310) 252-7105 data and specifications subject to change without notice. 3/18/2004
irmck203 application developer?s guide this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 2 table of contents 1 introduction ............................................................................................................................................................... 5 1.1 constraints .................................................................................................................... ..................................... 5 1.2 application connections ........................................................................................................ ........................... 5 2 concepts ....................................................................................................................... ............................................. 7 2.1 regulators ..................................................................................................................... .................................... 7 2.1.1 closed loop current control .................................................................................................... ................ 7 2.1.2 closed loop velocity control ................................................................................................... ............... 7 2.1.3 rotor angle estima tion ......................................................................................................... .................... 8 2.1.4 start-stop sequencer a nd fault detection ....................................................................................... .......... 8 2.2 current feedbacks .............................................................................................................. ............................... 8 2.2.1 using ir2175 ................................................................................................................... ......................... 8 2.2.2 using inverter leg shunt .......................................................................................................................... 8 2.3 communication .................................................................................................................. ............................... 8 2.3.1 rs-232 serial interface ........................................................................................................ ..................... 8 2.3.2 spi interface .................................................................................................................. ............................ 9 2.3.3 host parallel interface ........................................................................................................ ....................... 9 2.3.4 synchronization of pwm cycle to an external microprocessor ............................................................ 10 2.4 external interfaces ............................................................................................................ .............................. 10 2.4.1 discrete i/o exte rnal interface ................................................................................................ ................ 10 2.4.2 analog i/o interface ........................................................................................................... ..................... 11 2.5 sequencing control ......................................................................................................................................... 13 2.6 fault handling ................................................................................................................. ................................ 14 2.6.1 gatekill structure and overcurre nt/overtemperature fault .................................................................... 15 2.6.2 dc bus faults and dc bus braking ............................................................................................... ........ 15 2.7 led modes ..................................................................................................................................................... 16 3 motor start-up supporting tools ............................................................................................................................ 17 3.1 start-up flow .................................................................................................................. ................................. 17 3.1.1 drive parame ter setup .......................................................................................................... .................. 17 3.1.2 evaluating drive performance ................................................................................................... ............. 24 3.1.3 diagnostic mode functions ...................................................................................................... .............. 25 3.1.4 miscellaneous functions ........................................................................................................ ................. 28 3.2 standalone operation a nd register initialization via serial eeprom .......................................................... 31 3.2.1 register initializa tion via eeprom ............................................................................................. .......... 31 3.2.2 starting and stopping the motor ................................................................................................ ............. 32 3.2.3 fault pro cessing ............................................................................................................... ....................... 32 4 reference ...................................................................................................................... .......................................... 33 4.1 register access ................................................................................................................ ............................... 33 4.1.1 host parallel access ........................................................................................................... ..................... 33 4.1.2 spi register access ............................................................................................................ .................... 33 4.1.3 rs-232 regist er access ......................................................................................................... ................. 33 4.2 write register definitions ..................................................................................................... ......................... 38 4.2.1 pwmconfig register gr oup (write registers) ..................................................................................... ... 38 4.2.2 currentfeedbackconfig register group (write registers) .................................................................... 39 4.2.3 systemcontrol register group (write registers) ................................................................................. .. 40 4.2.4 torqueloopconfig register group (write registers) ............................................................................ 40 4.2.5 velocitycontrol register group (write registers) ............................................................................... .. 41 4.2.6 faultcontrol register gr oup (write registers) .................................................................................. .... 42 4.2.7 systemconfig register group (write registers) .................................................................................. .. 43 4.2.8 eepromcontrol register s (write re gisters) ...................................................................................... ...... 44 4.2.9 closedloopangleestimator regi sters (write registers) ........................................................................ 45 4.2.10 openloopangleestimator regist ers (write re gisters) .......................................................................... 46
irmck203 application developer?s guide this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 3 4.2.11 startupangleestimator regi sters (write registers) .............................................................................. .. 46 4.2.12 startupretrial register s (write re gisters) ..................................................................................... ......... 47 4.2.13 phaselossdetect register s (write re gisters) .................................................................................... ..... 49 4.2.14 d/aconverter registers (write registers) ....................................................................................... ....... 49 4.2.15 factory test register (write register) ......................................................................................... ........... 50 4.3 read register definitions ...................................................................................................... ......................... 51 4.3.1 systemstatus register group (read registers) ................................................................................... ... 51 4.3.2 dcbusvoltage register group (read registers) ................................................................................... .51 4.3.3 focdiagnosticdata register group (read registers) ............................................................................. 5 2 4.3.4 faultstatus register group (read registers) .................................................................................... ...... 53 4.3.5 velocitystatus register group (read registers) ................................................................................. ... 54 4.3.6 currentfeedbackoffset regist er group (read registers) ...................................................................... 55 4.3.7 eepromstatus register s (read re gisters) ........................................................................................ ....... 55 4.3.8 focdiagnosticdatasupplement regist er group (read registers) ........................................................ 56 4.3.9 productidentification regi sters (read registers) ............................................................................... .... 57 4.3.10 factory register (read register) ............................................................................................... ............. 57 appendix a space vector pwm module ............................................................................................ ....................... 58 svpwm basic theory and tr ansfer char acteris tics ................................................................................ .................. 58 pwm operation .................................................................................................................. ........................................ 60 pwm carrier period ................................................................................................................................................... 61 deadtime inser tion logic ....................................................................................................... ..................................... 61 symmetrical and asymmetr ical mode operation .................................................................................... ................... 61 three-phase and two-phase modulation ........................................................................................... ........................ 62 appendix b ir2175 current sensing ............................................................................................. ............................. 64
irmck203 application developer?s guide this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 4 list of figures figure 1. typical applicati on connections of irmck203 ......................................................................... ................. 6 figure 2. detailed control structure .......................................................................................... ................................... 7 figure 3. discre te i/o signals ................................................................................................ ..................................... 10 figure 4. analog interface example ............................................................................................ ............................... 12 figure 5. state diag ram and sequencing .................................................................................................................... 13 figure 6. protection ci rcuit block diagram .................................................................................... ............................ 15 figure 7. overview of drive commissioning ..................................................................................... ........................ 17 figure 8. motor information in user entries worksheet ......................................................................... ................... 18 figure 9. application informa tion in user en tries worksheet ................................................................... ................ 19 figure 10. shunt resistor valu e in user entr ies worksheet ..................................................................... ................. 22 figure 11. drive control modes ................................................................................................ ................................. 24 figure 12. parking diagnostic function ........................................................................................ .............................. 25 figure 13. enter optimal parking parameters ................................................................................... .......................... 26 figure 14. start-up diagnostic function ....................................................................................... .............................. 27 figure 15. open-loop start (ktorque = 400) .................................................................................... .......................... 27 figure 16. open-loop start-up (ktorque = 520) ......................................................................................................... 28 figure 17. enter optimal ktorque parameter .................................................................................... ........................ 28 figure 18. configuri ng the startup current .................................................................................... ............................ 30 figure 19. start-up retrial function .......................................................................................... .................................. 30 figure 20. irmck203 standalone system ......................................................................................... ........................ 31 figure 21. space vector diagram ............................................................................................... ................................ 58 figure 22. transfer characteristics ........................................................................................... .................................. 59 figure 23. voltage vector rescaling ........................................................................................... ............................... 59 figure 24. 3-phase space vector pwm ........................................................................................... ........................... 60 figure 25. 2-phase (6-step pwm) space vector pwm .............................................................................. ................ 60 figure 26. deadtime insertion ................................................................................................. .................................... 61 figure 27. asymme trical pwm mode .............................................................................................. .......................... 62 figure 28. three-phase and two-phase modulation ............................................................................... ................... 62 figure 29. different type s of space vector pwm ................................................................................ ..................... 63 figure 30. current feedb ack measurem ent block ................................................................................. ..................... 64 figure 31. current feedb ack calcula tion timing ................................................................................ ....................... 66 list of tables table 1. baud se lection table .................................................................................................. ..................................... 9 table 2. external rs- 232 signal description .................................................................................... ............................... 9 table 3. external spi i/f signal de scription ................................................................................... ................................. 9 table 4. external host para llel i/f signal description ......................................................................... .......................... 10 table 5. external inte rface signal de scription ................................................................................ ........................... 11 table 6. analog output data source selection .................................................................................. ......................... 12 table 7. sequenci ng control signals ........................................................................................... ............................... 13 table 8. drive fault conditions ............................................................................................... ................................... 14 table 9. overvoltage and undervoltage trip levels ............................................................................. ..................... 16 table 10. dynamic br aking voltage levels ...................................................................................... ......................... 16 table 11. led modes ........................................................................................................... ...................................... 16
irmck203 application developer?s guide this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 5 1 introduction this document is provided as a supplement to the datasheet for the irmck203. it provides detailed information about the internal design and external interfaces of the product and describe s how to configure the operation to conform to the requirements of a custom application. this document is intended for engineers who are developing an application using the irmck203 digital control ic. the document is divided into three main sections. in the concepts section, system design concepts are presented and theory of operation is described in detail. this section provides the background needed to begin irmck203 application development. the techniques section provides practical ?how-to? information, tips and examples to assist with the development process. the reference section provides a complete definition of the host register map with a short description of each register and field. the registers are listed in sequential order for easy reference. 1.1 constraints the following are constraints for use of the irmck203 with a custom hardware system. analog interface the irmck203 has a built-in interface to the ads7818 (bu rrbrown) serial a/d converter (12 bit). dc bus voltage feedback, external speed reference and leg shunt current can be obtained via ads7818 in conjunction with mux circuitry. an analog feedback application example is given in section 2.4.2. current feedback interface the irmck203 has a built-in interface ci rcuit for two ir2175 motor current se nsing high voltage ics. with two ir2175 and two shunt resistors, the motor phase current s can be obtained for motor control purposes. a 10-bit resolution of current feedback data can be obtained. the practical power level limit for using shunt resistors is up to 3.7 kw. for a higher horsepower application, a resi stor shunt becomes impractical due to power dissipation of shunt resistors (insert in series between motor and drive). the irmck203 provides other means of current feedback through the use of an ads7818 (burrbrown) serial a/d converter and inverter leg shunt resistor. inverter leg shunt currents can be used (reconstruction of phase current inside irmck203) instead of ir2175 current f eedback. however, the leg shunt option is recommended only for an inverter switching frequency less than 10khz. 1.2 application connections figure 1 shows a typical application connection block diagram. in order to complete a sensorless drive control, all necessary components are shown in connection to irmc k203. a fully self-contained drive evaluation board (irmcs2031) based on the irmck203 digital control ic is available for drive performance evaluation. the figure shows a typical hardware configuration. users can customize the design without the effort of modifying code.
irmck203 application developer?s guide t h is docum ent is the pr oper t y of i n ter n ational rectifier and m a y not be copied or distr i but ed without expr essed consent. 6 ir mck 2 0 3 di g i tal c o ntr o l ic tx rx es top fl t c l r sy n c fa u l t sc a hp d[ 0-7] hp oe n, hp w e n sc l re dle d sp i c lk sp i m iso sp i m osi sp i c sn o s c1 clk pwm u h pwm u l pwm v h pwm v l pwm w h pwm w l br ak e gate ki l l ifb0 ad c l k ad o u t a d co nv s t ad m u x0 moto r curre n t se ns ing to pc o p t i o nal m i c r oc on tro l l e r di scr e t e i/o swi t ch es se ria l ee prom bi -c ol or le d sy s t em cl o c k ir 2175 ir 2175 a d s7818 4051 ifb1 ad m u x1 po po 5v 5v 33m hz c r yst al gat e d r ive & igb ts i s olat or i s olat or fa u l tc l r mo t o r p h a s e sh unt mo t o r p h a s e sh unt spi in terf ac e max 2 32 a 80 51 up le d at 24c0 1a ana l og sp e e d re fe re nc e d c b u s vo ltag e da c0 da c1 da c2 da c3 an al og o u tp ut ba u d sel [ 1 :0] 2- leg sh unt c u rre n t se ns ing ( o pt i o na l) o s c2 clk hp cs n, hp a gr ee n l e d ad m u x2 r e ss am ple di r st ar t s top by pas sc lk by pas sm o d e pl ltes t ch g o lp vss pl l lo w pass fil t e r figure 1. ty pical application connections of irmck203
irmck203 application developer?s guide t h is docum ent is the pr oper t y of i n ter n ational rectifier and m a y not be copied or distr i but ed without expr essed consent. 7 2 concepts fi gure 2 shows t h e bl ock cont rol st ruct ure of t h e ir m c k203. 2.1 regulators 2.1.1 closed loop current control two proport i onal pl us int e gral (pi) t y pe current regul at ors wi t h out put l i m i t s and ant i - wi ndup cont rol are provi ded for t o rque and fl ux regul at i on of m o t o rs. torque current reference i s suppl i e d by speed regul at or out put and fl ux current reference is set to zero in or der to achieve the m a xim u m torque per am pere for a surface-mounted perm anent magnet m o tor. the current regulator outputs are m odulation depths. the m odulation depths are fed to a space vect or pw m m odul at or vi a a vect or rot a t o r (convert s dc t o ac waveform ). r e fer t o appendi x a for a descri pt i on of the space vector pw m m odule. 2.1.2 closed loop velocity control a pi speed regul at or wi t h out put l i m i t s (t orque current l i m i t ) and ant i - wi ndup cont rol i s provi ded for speed regulation. the speed reference is supplied by the ram p bl ock (as shown in figure 2). both speed acceleration rate and deceleration rate can be adj u sted. in addition, the ram p block provides m i nim u m speed protection in order to ensure opt i m al speed cont rol perform ance for sensorl e ss opera t i on. the r a m p bl ock i nput i s t h e user-desi r ed speed reference which can be obtained interna lly from the host register interface or ex ternally via the a/d interface as shown i n fi gure 2. det a i l s on how t o set up ext e rnal speed cont ro l m ode (st a ndal one m ode) are provi ded i n sect i on 3.2. ho s t con t r o ller i r 217 5 i r 217 5 i r m ck20 3 mot o r ac pow e r rs 23 2c or rs 42 2 cur r ent cur r ent j e j e 2/ 3 spe e d hos t r e gister inte rfa c e con f i g ur at i o n r e g i st er s moni t o r i ng r e g i st er s spi inte rfa c e spa c e vec t o r pw m (l o s s mi ni m i z a t i on) per i od /d u t y co unt er s per i od /d u t y co unt er s br ake fa u l t + - - + - + a/d in t e r f a c e a/ d mux se l e ct dc bus d y na m i c br ake co nt ro l a n a l og s peed ref e re nc e d c b u s f e ed b a ck p a ra lle l inte rfa c e i r 213 6 i r amy 20u p 60a p l ug-n- d r ive tm igbt modul e eepr o m rot o r a ngl e/ s p eed est i m a tor 4 c h ann el d/ a an alog mon i to r sp ee d ram p t o rq ue cur r e nt refer e n c e fl u x c u r r e n t refer e n c e star t-sto p s e q uen c e r an d f aul t det e c t or figure 2. detailed control structure
irmck203 application developer?s guide this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 8 2.1.3 rotor angle estimation motor shaft angle information is required for high pe rformance control of permanent magnet motors. the irmck203 sensorless control ic contains a motor shaft angle estimator, which provides shaft angle and motor speed information. there is no need for encoder or hall sensor element feedback. 2.1.4 start-stop sequencer and fault detection a start-stop sequencer provides total drive sequencing for handling start-stop and start-up failure retry functions. there are various fault triggers (detailed in section 2.6) to ensure that the drive is protected under various fault conditions. 2.2 current feedbacks 2.2.1 using ir2175 two channels of current feedback interface logic are provided in the irmck203. each module measures the incoming varying duty period of the 130 khz carrier frequency signal at the ir2175 output. measurement is performed for both carrier frequency pe riod and on duty period at the same time using fast counters. counting frequency is 133 mhz with a 33.3 mhz system clock. the ir2175 is the unique high voltage ic capable of measuring the motor phase current through an associated shunt resistor, which can generate 260mv voltage range. the output of the ir2175 is an open drain with a 130 khz fixed carrier frequency where the duty variance is linearly proportional to 260 mv input voltage. the counting frequency is 133.3 mhz when the system clock crystal frequency is 33.3 mhz, which yields 10-bit resolution of the current measurement data from the ir2175. a more detaile d description of the ir2175 can be found in appendix b. 2.2.2 using inverter leg shunt the irmck203 provides another means of current feedback through the use of an ads7818 (burrbrown) serial a/d converter. inverter leg shunt (install in low side) curre nts can be used instead of ir2175 current feedback for sensorless motor control. the minimum requirement is two leg shunt feedbacks (v and w phases). an application example is given in section 2.4.2 for interfacing leg shunt currents to the irmck203 digital control ic. in the irmck203, the selection of current feedback is done via a user configuration parameter (provided in the motor commissioning tools). the leg shunt option is recommended for inverter switching frequencies less than 10khz. 2.3 communication the irmck203 contains a rich set of externally addressabl e "host" registers documented in section 4 of this guide. there are three physical interfaces that can access the host registers: rs-232, spi and host parallel. 2.3.1 rs-232 serial interface the slowest of the three, the serial interface, is used for inter-board comm unications typically using cables as the connection medium. the irmck203 implements an error detecting protocol la yer that facilitates maintaining the integrity of the host registers. prior to updating any host register, the incoming data must match a checksum string to detect single bit errors. please refer to the rs-232 protocol documentation in section 4.1.3 for the specific protocol definition. the rs-232 seri al interface supports four baud rates ba sed on the signal levels on pins 30 and 42 of the irmck203, as shown in table 1.
irmck203 application developer?s guide this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 9 baudsel1 pin 42 baudsel0 pin 30 resulting baud selection 0 or low 0 or low 19.2 k baud 0 or low 1 or high 38.4 k baud 1 or high 0 or low 57.6 k baud 1 or high 1 or high 1 meg baud table 1. baud selection table the rs-232 interface implements a byte serial physical layer in addition to an error checking protocol layer. the coding of the bit-serial data is us ascii, 8 data bits, 1 stop bit and no parity. table 2 describes the physical laye r signals of the rs-232 interface. signal name direction description tx output a bit-serial signal originated by the irmck203 in response to a microprocessor-generated request. rx input bit-serial data sent to the irmck203 by the microprocessor to interrogate one of the host registers. table 2. external rs-232 signal description 2.3.2 spi interface the spi interface is also a byte serial interface, but can operate at much gr eater transfer rates than the rs-232 interface. bit rates of up to 8 mhz can be achieved. the spi interface performs a serial byte read and write in a "full duplex" mode. refer to the spi access documentation in sec tion 4.1.2 for the protocols required to access the host registers, and the spi timing section of the irmck203 datasheet for the physical layer specifications. table 3 describes the physical laye r signals of the spi interface. signal name direction description spiclk input serial clock generated by the spi master logic. spimosi output serial data: master input and slave output. spimiso input serial data: master output and slave input. spicsn input chip select signal. used to qualify the spiclk, spimiso and spimosi signals. table 3. external spi i/f signal description 2.3.3 host parallel interface designed to transfer bytes in a bit paralle l fashion, this is the fastest interface of the three. the ho st parallel interface is compatible with all popular microprocessors, including motorola and intel based bus protocols. refer to the parallel access documentation in section 4.1.1 fo r the protocols required to access the ho st registers, and the host parallel timing section of the irmck203 datasheet for the physical layer specifications. table 4 describes the physical layer si gnals of the host parallel interface.
irmck203 application developer?s guide t h is docum ent is the pr oper t y of i n ter n ational rectifier and m a y not be copied or distr i but ed without expr essed consent. 10 si gnal name direction description hp_noe input w h en l ogi c l o w, or 0, i ndi cat es t h e begi nni ng of a paral l e l dat a t r ansfer cy cl e. hp_nw e input w h en l ogi c l o w, or 0, i ndi cat es t h at t h e dat a / a ddress t r ansfer cy cl e i s a wri t e cy cl e, wi t h dat a bei ng sourced by t h e m i croprocesso r. w h en high, the data cycle is a read cy cl e, wi t h dat a bei ng sourced by t h e ir m c k203 hp_d [7: 0 ] input / o ut put an 8-bi t wi de dat a bus. hp_a input address at t r i but e si gnal . w h en hi gh, or a l ogi c 1, i ndi cat es t h at t h e dat a on t h e hp_d[7: 0 ] bus i s a address t o be l o aded i n t o t h e ir m c k203 address regi st er. table 4. external host parallel i/f signal description 2.3.4 synchronization of pwm cycle to an external microprocessor a dedi cat ed sync si gnal i s provi ded on t h e ir m c k203 (pi n 52) t h at al l o ws sy nchroni zat i on of t h e i n t e rnal ir m c k203 l ogi c t o an ext e rnal m i croprocessor. thi s sy nchroni zat i on i s useful when ext e rnal m i croprocessor control loops are im plem ented. also, an external trace bu ffer could be im plem ented to interrogate various nodes in the irmck203 while the irmck203 is actively controlling the m o tor. the sync signal has a long pulse width suitable to connect to an edge or level sensitive m i croprocessor interrupt i nput pi n. the l o w goi ng edge of t h i s pul se i s an i ndi cat i on t o t h e m i croprocessor t h at t h e ir m c k203 i s st art i ng a new pw m cy cl e. r e fer t o t h e adc sy st em level ti m i ng sect i on of t h e ir m c k203 dat a sheet for speci fi c t i m i ng inform ation. both the spi and host parallel interfaces are suitable for pw m cycle and trace buffer synchronization. the sync signal offers the m i croprocessor a tim ing window to access the entire host register set. the num ber of sync pul ses per pw m l o ad can be confi gured us i ng t h e support t ool s descri bed i n sect i on 3. the sync pul se wi dt h i s sui t a bl e for connect i ng opt o-i s ol at i on ci rcui t r y bet w een t h e ir m c k203 and t h e m i croprocessor. 2.4 external interfaces this section describes the external interfaces supported by the irmck203 in addition to the host register interface described in section 2.3. these incl ude the discrete i/o interface used for standalone operation and the analog i/o interface provided for diagnostic purposes. 2.4.1 discrete i/o external interface the discrete i/o external interface signa ls provide a m eans of controlling basi c m o tor operation without using the host register interface. in this m ode of opera tion, the analog reference (described later in this section) is used to directly control the target speed. fi gure 3 shows a schem a t i c di agram of t h e di scret e i/ o si gnal s . the si gnal s are descri bed i n tabl e 5. irmc k203 digital control ic startstop dir es top fltclr faul t sy nc disc re te i/o s figure 3. discrete i/o signals
irmck203 application developer?s guide this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 11 signal name direction description startstop input motor start/stop control. a positive edge transition of this signal starts the motor and a negative edge transition stops the motor. dir input motor direction control. 1 = forward, 0 = reverse. this signal is latched when the motor is started, so that changing it while the motor is running has no effect. estop input emergency stop. when this signal is set to ?1?, pwm is unconditionally disabled. this signal overrides the start/stop control fltclr input a 1 sec pulse on this signal cl ears a drive fault condition. equivalent to setting the fltclr bit of the faultcontrol register (see section 4.2.6). fault output this signal indicates the presence of a drive fault condition. the level is high when any of the bits in the faultstatus register are set (see section 4.3.4). sync output this signal is held low fo r 2 sec on each pwm period. (the falling edge indicates the start of the pwm period.) table 5. external interface signal description note: when the extctrl bit in the systemconfig register is set to ?0?, the estop and negative edge of the start/stop signals are functional, but all ot her external interface signals are inactive. to configure the discrete i/o interface, wr ite a ?1? to the extctrl b it in the systemconfig host write register to enable the external interface pins. (refer to section 4.2.7 fo r more information about th e systemconfig register.) 2.4.2 analog i/o interface irmck203 provides analog input capability through the use of the ads7818 a/d converter and mux circuitry. the intended inputs are speed reference, dc bus vo ltage and two inverter leg shunt currents. analog input figure 4 shows the typical hardware c onfiguration for the analog input interface. the multiplexor input a0 (shown on the diagram) accepts voltages in the ra nge 0 ? 5v, with two possible mappings: ? 2.5v = zero speed (0 digital count), 0v = max speed (16, 383 digital count) ? 2.5v = zero speed (0 digital count), 5v = max speed (16, 383 digital count) the example implements the first of the two mappings (0v max speed), supplying a +15 volt analog reference for an external variable resistor. (the dir signal contro ls the motor direction, as described in table 5.) in this example circuit, the irmck203 automatically scans through a/d conversion of all four channels at the beginning of each pwm cycle (sync output). the v and w phase currents followed by dc bus voltage and speed reference are scanned in. in this example, the dc bus feedback gain is 100 times attenuation. the leg shunt amplifier gain for this example is 7.97 and the a/d convert er scaling is 4095 digital counts per 5v. this information is required during drive commissioning for scaling of dc bus voltage and current feedback. leg shunt feedback can be eliminated if ir2175 is inte nded for current feedback. the interface to the ir2175 is straightforward and can be found in the ir2175 data sheet.
irmck203 application developer?s guide t h is docum ent is the pr oper t y of i n ter n ational rectifier and m a y not be copied or distr i but ed without expr essed consent. 12 10 + 22uf,10v vref 1 gnd 4 conv 5 data 6 clk 7 +vcc 8 +in 2 -in 3 ads7818eb 0.1uf 0 a/d, dc bus voltage sensing & resolver i/f to irmck203 0.1uf + 10uf,10v a0 13 a1 14 a2 15 a3 12 e 6 vdd 16 gnd 8 vee 7 s1 10 s2 9 out 3 s0 11 a4 1 a5 5 a6 2 a7 4 cd74hct4051m - + 10 9 8 4 11 tlv2374id 1000pf + 10uf,10v 1 2 14 7 13 cd74hct4066m 1000pf 8 9 6 cd74hct4066m 0.1uf - + 5 6 7 4 11 tlv2374id 1 i_v 1 i_w 5.11k, 1% 48.7k, 1% 5.11k, 1% - + 10 9 8 4 11 tlc2274 1.00k, 1% 48.7k, 1% 1.00k, 1% 47pf, 50v 5.11k, 1% 48.7k, 1% 5.11k, 1% - + 5 6 7 4 11 tlc2274 1.00k, 1% 48.7k, 1% 1.00k, 1% 47pf, 50v - + 5 6 7 4 11 tlv2374id 0.1uf 1000pf 1.00m, 1% 10 10k 909k, 1% 2200pf,50v 10 50k 20.0k, 1% + 22uf,10v - + 3 2 1 4 11 tlv2374id 90.9k, 1% - + 3 2 1 4 11 tlc2274 1k 1k 100pf + 22uf,10v 0.1uf a a a a a a a a a a a a a a a a a a a a a a 1 1 3 2 50k a +5v ad_out ad_clk ad_convst +5v mux_s0 mux_s1 mux_s2 +5v +5v +5v +5v 2.5v_ref_buf i_w +5v 2.5v_ref_buf i_v ressample dcbus_fb +5v +5v dc+ +5v 2.5v_ref_buf 2.5v_ref_buf +15v analog ref figure 4. analog interface example anal og output the diagnostic d/a interface provides four sources of diagnostic data and is inte nded for use with external rc filters fo r o s cillo sco p e d i sp lay. th e u s er can select o n e o f fo u r sets o f d a ta so u r ces b y settin g th e v a lu e o f th e dacsel regi st er i n t h e d/ ac onvert er wri t e regi st er group (see sect i on 4.2.14) as shown i n tabl e 6. dacse l value selected data sources 0 f l u x 1 r o t o r angl e 2 t o r q u e current 0 3 c l osed l oop st at us 0 dc bus vol t a ge 1 a l pha vol t a g e 2 torque current reference 1 3 m o t o r s p e e d 0 q-axi s com m a nd vol t a ge 1 d-axi s com m a nd vol t a ge 2 a l pha current 2 3 b e t a current 0 f l ux m a gni t u d e 1 current error at parking 2 parki ng di agnost i c fl ag 3 3 w - phase current table 6. analog output data source selection each si gnal i s encoded as a pul se-wi d t h m odul at ed 8- bi t val u e out put at a frequency of 128 khz. therefore, hardware filtering is required to require to extract the actual signal. the data values are updated on each sync pulse. the values for each data source are scaled so that the valid range is represen ted as an 8-bit unsigned value. for
irmck203 application developer?s guide t h is docum ent is the pr oper t y of i n ter n ational rectifier and m a y not be copied or distr i but ed without expr essed consent. 13 exam pl e, t h e val u es of q-axi s and d-axi s com m a nd vol t a ge, whi c h have an act ual range of ?16,384 t o 16,383, are rescal ed t o t h e range 0 ? 255 (so t h at 0 represent s ?16,384 and 255 represent s 16, 383). 2.5 sequencing control sequencing control is provided in the irmck203 system to facilitate basic i/ o sequencing. the signals shown in table 7 can be directed either by local discrete i/o pins or the host register in terface. stop is always activated by either the host interface register or the local start/stop input pin. si gnal description start start m o tor signal from host or external user interface. stop start m o tor signal from host or external user interface. estop thi s si gnal , whi c h i s not shown i n fi gure 1, st ops t h e m o t o r uncondi t i onal l y regardless of the state. fault indi cat es a pendi ng fault condi t i on. it i s cl eared upon fltc lr assert i on. fltc lr c l ear pendi ng fault. start ok signal from startup control m odule th at indicates a successf ul startup occurred startup fault indicates a fa iled startu p attem p t o ccu rred r e t r i e s r unni ng count of t h e num ber of ret r i e s at t e m p t e d duri ng t h e st art up sequence. m a x r e t r i e s user program m a bl e regi st er set t i ng i ndi cat i ng t h e m a xi m u m num ber of ret r i e s. the m a xi m u m val u e of ret r i e s can be 16. r e t r y i s di sabl ed when t h i s val u e i s 0. overvol t a ge undervol t a g e overcurrent overspeed faul t condi t i ons. table 7. sequencing control signals internally, the irmck203 has three states : stand-by or stop state, run st ate, and fault state. transitioning to each state can be caused either by in itiation of the i/o pins desc ribed above or internal drive conditions such as overcurrent , overvol t a ge, et c. the st at e di agram i s shown i n fi gure 5. s t andb y or st o p run fau l t p o w e r- up st ar t st o p o v er c u r r ent o v er v o l t age u nder v o l t age o v er speed o v er v o l t age u nder v o l t age flt c lr par k/ st ar t u p re t r y st a r t o k re t r i e s < ma x r e t r i e s st a r t u p faul t re t r i e s > = ma x r e t r i e s figure 5. state diagram and sequencing
irmck203 application developer?s guide this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 14 2.6 fault handling the irmck203 system has built-in drive fault and protection features. table 8 summarizes the types of drive fault conditions. fault status indication on host register interface description overcurrent /overtemperature fltstatus read register, field gatekillflt = 1 overcurrent or overtemperature occurred. the igbt gate driver (ir2136) disables gate drive outputs, momentarily latches a fault condition and asserts gatekill to the irmck203. this activates the fault latch inside the irmck203. overvoltage fltstatus read register, field ovflt = 1 overvoltage of the dc bus occurred. only the fault latch inside the irmck203 is activated. overspeed fltstatus read register, field ovrspdflt = 1 the speed of the motor exceeded th e maximum speed. only the fault latch inside the irmck203 is activated. overrun fltstatus read register, field exectmflt = 1 the computation of algorithm exceed ed the selected pwm carrier frequency period. only the fault latch inside the irmck203 is activated. low voltage fltstatus read register, field lvflt = 1 the bus voltage dropped below a certain level (determined by the dc bus feedback scaling). only the fault latch inside the irmck203 is activated. zero speed fltstatus read register, field zerospdflt = 1 when speed is less than minspd/2 (half minimum speed) for a continuous period of 2 seconds, the zero speed fault occurs. only the fault latch inside the irmck203 is activated. startup retry failure fltstatus read register, field retryflt = 1 after a configured number of start-up failures (determined by register numretries in the startupretrial write register group), this fault occurs. only the fault latch inside the irmck203 is activated. phase loss fltstatus read register, field phslossflt = 1 this fault indicates that the drive to motor phase connection may be loose. only the fault latch inside the irmck203 is activated. table 8. drive fault conditions when any drive fault occurs, the pwm output is disabled and the gate signals from the irmck203 device are negated. this condition remains latched until fault_clear action is undertaken by the user. fault_clear, a level sensitive signal event, can be initiated e ither through the fltclr b it in the faultcontrol host register or the fltclr discrete i/o external interface pin. fo r more information about th e faulcontrol and faultsta tus registers, refer to sections 4.2.6 and 4.3.4, respectively. when a fault occurs, the led indication is as follows: redled = 1, greenled = 0.
irmck203 application developer?s guide t h is docum ent is the pr oper t y of i n ter n ational rectifier and m a y not be copied or distr i but ed without expr essed consent. 15 2.6.1 gatekill structure and over current/overtem perature fault for exam ple, the irmcs2031 design platform for irmck203 has an a dvanced intelligent power m odule (ir am x16up60a) rat e d at a 600v/ 16a. thi s igb t m odul e cont ai ns an i n t e grat ed hi gh vol t a ge gat e dri v e ic (ir 2136) wi t h a t h erm i st or. a ground faul t prot ect i on ci rcui t i s al so equi pped on t h e ir m c s2031. the si gnal i s fed t o an opt o-coupl er devi ce t o t r i gger t h e si gnal t o ir m c k203 pi n 37, gatekill. w h en an overcurrent condi t i on occurs, gatekill i s assert ed and m o m e nt ari l y l a t c hed wi t h i n t h e ir 2136 for t h e program m e d period, which is approxim a tely 9 m illiseconds. after this period, the pending fault is autom a tically cl eared. m eanwhi l e , t h e t r i ggered gatekill assert i on l a t c hes and i nhi bi t s al l pw m out put gat e si gnal s off t h e irmck203 until the user initia tes a fault clear action. i r a m x16up60a ir m c k203 ir2136 opt o gro und fau l t pr ot ec t i on dc bus (+) dc bus (-) g a t eki ll rc in opt o in pu t pw m out put 6 to mo t o r ov ert e m p figure 6. protection circuit block diagram fi gure 6 shows t h e prot ect i on ci rcui t di agram . the igb t m odul e cont ai ns an r c ci rcui t connect ed t o r c i n i nput of the ir2136, which autom a tically initiate s fault clear in 9 m illiseconds after assertion of fault. the igbt m odul e al so cont ai ns an overt em perat u re prot ect i on ci rc ui t , whi c h shut s down al l igb t s and perform s aut o m a t i c fault c lear as wel l . overt e m p erat ure prot ect i on can be enabl e d by addi ng a 6.8 kohm ext e rnal resi st or. the t h reshol d l e vel i s set at approxi m a t e l y 110 ?? 2.6.2 dc bus faults and dc bus braking the dc bus si gnal i s em pl oy ed for dc bus overvol t a ge, under vol t a ge prot ect i on and b r ake cont rol . it i s al so used for com p ensat i on of m o t o r cont rol l e r scal i ng i n t e rnal t o t h e ir m c k203. it i s cruci a l t o desi gn a sui t a bl e dc bus feedback scal i ng for proper dri v e prot ect i on. the dc bus vol t a ge can be acqui red vi a t h e ads7818 a/ d convert er. the i nput of ads7818 m a ps 0 - 5 vol t s i n t o 0 - 4095 di gi t a l count s. the overvol t a ge and undervol t a ge t r i p l e vel s are gi ven i n tabl e 9. the anal og scal i ng (am p l i f i e r gai n ) of t h e dc bus i s rest ri ct ed by t h e desi red vol t a ge t r i p l e vel s . therefore, t h e si gnal condi t i oni ng (am p l i f i e r gai n ) of dc bus voltage feedback needs to be considered carefully.
irmck203 application developer?s guide this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 16 dc bus feedback irmck203 internal digital counts (fixed) ads7818 input voltage actual dc bus voltage (assumption: amplifier gain 1/100 ) overvoltage trip fault 3360 4.1 v 410v undervoltage trip fault 976 1.2 v 120v undervoltage clear level 1152 1.4 v 140v table 9. overvoltage and undervoltage trip levels some applications may require power regeneration. under such circumstan ces, an external braking circuit (for dynamic braking) can be used to absorb regeneration energy from the motor. the irmck203 provides braking control. the braking control utilizes dc bus voltage feedback to determine when to activate and release the braking circuit. the dynamic braking voltage level is given in table 10. the analog scaling (amplifier gain) of the dc bus presets the brake on-off levels. brake condition dc feedback digital counts (fixed) ads7818 input voltage actual dc bus voltage (assumes amplifier gain 1/100) brake turn on 3120 3.8 v 380v brake turn off 2944 3.6 v 360v table 10. dynamic braking voltage levels 2.7 led modes the operating state of the irmck203 is indicated by the led module. there are three indication modes. mode 1 indicates successful configuration of the irmck203. the led is green in this mode. thus, a green led appears automatically right after power up. a red led indicates a drive fault condition. this is mode 2. the led is not lit in mode 3. this is a hardware fault condition. this means that e ither configuration data was not transferred to irmck203 correctly or the irmck203 itself has a hardware problem. mode led indication description mode 1 green irmck203 configuration has been done correctly and irmck203 is functioning normally. mode 2 red a drive fault condition is pending. mode 3 off irmck203 is not functioning indicating either configuration is not completed correctly and/or irmck203 has a hardware problem itself. table 11. led modes
irmck203 application developer?s guide t h is docum ent is the pr oper t y of i n ter n ational rectifier and m a y not be copied or distr i but ed without expr essed consent. 17 3 motor start-up supporting tools 3.1 start-up flow aft e r peri pheral ci rcui t r y has been i m pl em ent e d for t h e cont rol ic , a st art - up procedure i s provi ded t o gui de t h e user t h rough t h e com m i ssi oni ng of t h e user?s m o t o r appl i cat i on. c onfi gurabl e param e t e rs are requi red t o t a i l o r t h e desi gn t o vari ous appl i cat i ons (m ot or and l o ad). these confi gurabl e param e t e rs can be m odi fi ed vi a t h e host regi st er interface (using the servodesigner tool) through the co m m unication interface. a de sign spreadsheet (drive param e t e rs t r ansl at or) i s provi ded t o ai d t h e user for ease of dri v e st art - up. usi ng t h e spreadsheet, the user enters hi gh-l e vel param e t e rs such as m o t o r nam e pl at e i n form a t i on, m a xi m u m appl i cat i on speed, current l i m i t , speed and speed regul at or bandwi d t h . thi s hi gh-l e vel user i n form at i on is tran slated to en g i n eerin g p a ram e ters (d irectly u s ed by t h e dri v e). fi gure 7 gi ves an overvi e w of t h e com m i ssi oni ng st eps. dr iv e p a r a m e ter s t r a n slato r ( s pr ea d s h e e t pr ogr a m ) t r an s l at e u ser h i g h lev e l in p u t p a r a m e ter s t o d i g ital d o m a i n p a r a m e ter s (e n g in eer i n g) e n te r h i g h l e v e l des i gn pa r a m e t e r s (m ot o r n a m e p l ate, c u r r en t l i m i t s , m a x s p e e d , o v er lo ad etc . .) e n g i n e er in g pa r a m e t e r s i r m c k 2 0 3 b a sed p l atf o r m s e r v o d esig n er i n pu t e n gi n e e r i n g pa r a m e t e r s a n d dow n l oa d t o i r m c k 2 03 dr i v e pl a t f o r m user pa r a m e t e r s figure 7. ov erv i ew of driv e commissioning 3.1.1 drive param e ter setup the ir m c k203 support soft ware i n cl udes an excel workbook fi l e t h at part i a l l y aut o m a t e s t h e procedure of cal cul a t i ng t h e appropri a t e val u es for confi gurat i on and t uni ng param e t e rs. in t h e workbook, t h e user ent e rs m o t o r nam e pl at e dat a and param e t e rs speci fi c t o hi s appl i cat i on, and excel form ulas calculate t h e appropri a t e val u es for cert a i n wri t e regi st ers. in excel , t h e ?save as?? funct i on i s used t o export t h e regi st er val u es t o a t e xt fi l e , and i n serv o d esig n e r, th e tex t file can b e im p o r ted to fill in th e reg i ster v a lu es. th en , wh en th e co n f ig u r e mo to r fu n c tio n is executed in servodesigner, the values ar e written to the irmck203 based platform . the excel workbook file the excel workbook fi l e i s nam e d ir m c s2031-dri v eparam s.xl s. doubl e cl i c k t h e fi l e t o open i t i n excel . at t h e bot t o m of t h e workbook wi ndow, t h ere are t w o sheet t a bs, whi c h sel ect t h e worksheet t o be di spl a y e d. the first tab selects th e ?user en tries? wo rk sh eet u s ed to set u p m o to r an d ap p licatio n p a ram e ters. th is sh eet is p r e- initialized with values appropriate fo r the sanyo denki 400w 3000rpm m o tor and is provided as an exam ple. the ?user entries? worksheet can be custom ized fo r an y m o to r. to calcu late settin g s fo r m o re th an o n e m o to r, m a k e copies of the irmcs2031-driveparam s.xls file and m odify each copy to defi ne a different m o tor.
irmck203 application developer?s guide t h is docum ent is the pr oper t y of i n ter n ational rectifier and m a y not be copied or distr i but ed without expr essed consent. 18 the second t a b i s l a bel e d ?param et er export . ? thi s worksheet shows t h e cal cul a t e d wri t e regi st er val u es and i s t h e sheet t h at needs t o be export e d for use i n servodesi gner. enter motor and applicat ion parameters in excel the first stage of configuring drive pa ram e ters involves entering the correct se ttings for a specific m o tor and custom appl i cat i on requi rem e nt s. step 1. initializ e a motor setup sheet for the motor. c l i c k on t h e ?user ent r i e s? sheet t a b t o sel ect t h e m o t o r set up worksheet . if desi red, doubl e-cl i c k t h e sheet t a b and change the tab title to identif y the m o tor. the first line of the m o tor setup worksheet describes the m o tor. double cl i c k on col u m n b and ent e r a descri pt i on of t h e m o t o r. (t he descri pt i on i s opt i onal ; i t ? s not used i n t h e cal cul a t i ons and i s not export e d t o servodesi gner.) step 2. enter motor information. the m o t o r i n form at i on sect i on of t h e ?user ent r i e s? worksheet cont ai ns param e t e r set t i ngs t h at shoul d be avai l a bl e i n the m o tor?s datasheet or on its nam e plate. to enter a value for each param e ter, double click in colum n b on the sam e line as the param e ter nam e . w h en the m ouse is m oved over colum n b for each param e ter, a short description of t h e param e t e r i s shown i n a hel p bubbl e. figure 8. motor information in user entries worksheet m o re det a i l e d descri pt i ons are provi ded bel o w. hz the rat e d frequency of t h e m o t o r (i n hert z). rpm the rated speed of the m o tor (in rpm). lq m o t o r per phase i nduct a nce (i n henry ) . r_stator per phase resistance of the m o tor plus cabl e (i n ohm s). amps the rated current of the m o tor (in am ps rm s). inertia to tal in ertia (m o t o r in ertia p l u s lo ad in kg -m 2 ). if to tal lo ad in ertia is n o t specified in the available design data, use a best estim ate and adjust the value later when fi ne-t uni ng dri v e operat i on (refer t o sect i on 3.1.2). kt m o t o r t o rque const a nt (i n newt on-m e t e r per am ps rm s).
irmck203 application developer?s guide t h is docum ent is the pr oper t y of i n ter n ational rectifier and m a y not be copied or distr i but ed without expr essed consent. 19 ke m o t o r vol t a ge const a nt (i n l i n e-t o -neut r al rm s vol t s per t housand rpm ) . not e t h at so m e m o to r m a n u f actu r ers p r o v i d e d a ta in lin e-to -lin e rm s v o lts, in wh ich case th e val u e m u st be convert ed t o l i n e-t o -neut r al vol t a ge. poles the num ber of m o t o r pol es. step 3. enter application information th e ap p licatio n in fo rm atio n sectio n o f th e ?user en tries? worksheet cont ai ns param e t e r set t i ngs t h at descri be t h e requirem e nts of a specific app lication. the param e ters are described belo w. to enter a value for each param e ter, doubl e cl i c k i n col u m n d on t h e sam e l i n e as t h e param e t e r nam e . figure 9. application information in user entries worksheet max rpm thi s i s t h e m a xi m u m speed (i n rpm ) requi red for t h e appl i cat i on. w h en m o t o r speed exceeds this value, the system will generate an over speed trip fault. it is suggest ed t h at t h i s val u e be set t o t h e rat e d speed of t h e m o t o r pl us 20 percent .
irmck203 application developer?s guide this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 20 nominal vdc nominal dc bus voltage (in volts). for use with the irmcs2031 development platform, the nominal dc bus voltage should be set to 1.414 * ac input voltage ( ac input voltage: usa 110v, jap 100v, uk 220v etc.). max overload current this is the anticipated maximum current in per unit drawn by the motor at the motor?s rated speed. setting this parameter to 1 pu means that the system drives 100% rated current at the rated speed. speed regulator bw speed regulator bandwidth (in rad/sec). the system may not tolerate high speed regulator bandwidth (due to mechanical c oupling, gear box etc.), resulting in load mechanical resonance. if the correct setting for this parameter is not known, start with a value of 10 rad/sec and raise it gradually as the system is tuned. typical values would range between 10 and 25 rad/sec. acceleration rate this parameter defines the number of s econds required for the motor to accelerate from 0 speed to the motor?s rated speed. deceleration rate this parameter defines the number of s econds required for the motor to decelerate from rated speed to 0 speed. motoring limit positive torque current limit (in percentage of rate current). motoring power is energy transferred from the inverter to the motor while the motor is running. regen limit negative torque current limit (in percen tage of rate current). regenerative energy is transferred from the motor to th e inverter when the motor decelerates. if the system does not contain a breaking resistor to absorb the regenerative energy, an increase in dc bus voltage (and potential trip fault) results. this parameter should be set to zero if the system cannot absorb regenerative power, which is the case for the irmcs2031 development platform as shipped. drive start current limit drive start-up current. during initial drive start-up, this current limit will be applied to ensure robust start-up. input as percentage of rated motor current. minimum running speed this is the minimum allowable operating speed for the sensorless drive. typical values range between 5% and 10% of rated motor speed. pwm carrier freq pwm carrier frequency. 10 khz is the default setting for the irmcs2031 product. the setting of this parameter is a tradeoff between current ripple, inverter loss and emi noise. drive peak amps this parameter defines the anticipated maximum drive current. this parameter should be chosen to accommodate the anticipated full current range. the current feedback resolution will degrade as a consequence of using a higher drive peak amps value. therefore, it is best to choose the minimum value that satisfies the requirements of the application. it may be necessary to change the current feedback shunt resistor on the irmcs2031 development platform to conform to the setting of this parameter. a shunt value calculated and displayed on the worksheet to the right of the drive p eak amps entry (column f) shows the recommended resistor value. it may be necessary to adjust the setting of the drive peak amps parameter slightly to obtain a shunt recommendation that corresponds to a commercially available resistor value (1% or less tolerance recommended).
irmck203 application developer?s guide t h is docum ent is the pr oper t y of i n ter n ational rectifier and m a y not be copied or distr i but ed without expr essed consent. 21 stopping mode the dri v e st oppi ng m ode can be confi gured usi ng t h i s param e t e r. co ast sto p (en t er 0 ) : wh en sto p co m m a n d is issu ed , th e in v e rter will switch o ff im m e d i ately. th e m o to r sp eed will b e d ecreased b y win d a g e an d frictio n . ram p sto p (en t er 1 ) : w h en sto p co m m a n d is issu ed , th e in v e rter will co n t ro l th e m o tor speed down to zero. the rate of stopping is determ ined by the setting of deceleration rate and regen current lim it. no te: ram p sto p will reg e n e rate en erg y b ack to th e d c b u s , h e n ce will in crease d c bus voltage during fast deceler ation, please ensure brake is installed if ram p stop m ode i s used. step 4. enter advance information (hardware dependent) the advanced i n form at i on sect i on of t h e m o t o r set up worksh eet cont ai ns param e t e r set t i ngs that are specific to the hardware platform . it i s not necessary to modi fy these setti ngs for use w i th the irmcs2031 devel o pment platform. deadtime th is p a ram e ter sets th e in v e rter d ead tim e d e lay. th e en ter u n it is in u s ec. th e set t i ng depends on what t y pe (igb t , m o sfet et c..) of m a i n power swi t c hes bei ng used i n t h e i nvert er. users shoul d refer t o t h e deadt i m e val u e suggest ed by t h e power devi ce m a nufact urer. dc bus scale t hi s i s t h e dc bus scal i ng i n di gi t a l count s per vol t of dc bus. the i n form at i on i s t h e hardware scal i ng of dc bus feedback. for instance: if user' s hardware scales down the dc bus 100 tim es, then at 500 v dc bus level, 5v will appear at the a/d convert er (ads7818) i nput . the ads7818 m a ps 5v (at vcc = 5) t o 4095 di gi t a l count s. therefore, t h e b u s scal i ng i s 4095/ 500 = 8.19 ct s/ v. i shunt thi s param e t e r provi des current feedback sel ect i on. pl ease ent e r "0" i f usi ng ir 2175 , "1" i f usi ng invert er leg shunt amp gain thi s param e t e r i s onl y requi red i f leg shunt i s sel ect ed as t h e current feedback choi ce, and speci fi es t h e am pl i f i e r gai n from leg shunt sam p l i ng resi st or t o i nput of a/ d convert er. for i n st ance, i n t h e hardware exam pl e gi ven i n sect i on 2.4.2, t h e leg shunt am pl i f i e r gai n i s 7.97.
irmck203 application developer?s guide t h is docum ent is the pr oper t y of i n ter n ational rectifier and m a y not be copied or distr i but ed without expr essed consent. 22 export drive parameters in excel in the second stage of configuring drive param e ters, the param e ter settings selected in the previous section are used to calculate values for a num ber of irmck203 write registers. the write register va lues are written to a text file in a specific form at defined for use wi t h servodesi gner. step 1. note shunt resistor value at t h e bot t o m of t h e ?user ent r i e s? worksheet , not e t h e cal cul a t e d current feedback shunt resi st or val u e shown i n colum n f (see figure 10). if the value shown does not corre spond to an available resistor, it m a y be necessary to m odi fy t h e ?dri ve peak am ps? set t i ng. aft e r m odi fy i ng t h e val u e, check t h e shunt resi st or val u e agai n. figure 10. shunt resistor value in user entries worksheet step 2. save the settings w h en al l param e t e rs are set appropri a t e l y , sel ect save fro m excel ?s fi l e m e nu t o save t h e workbook fi l e i n ?.xl s? form at. step 3. export drive parameters c l i c k on t h e param e t e r export t a b at t h e bot t o m of t h e workbook wi ndow. thi s worksheet shows t h e regi st er val u es th at were calcu lated settin g s were ch an g e d in th e m o to r setup worksheet. from excel?s file m e nu, select ?save as??. in t h e save as di al og, sel ect sa ve as t y pe: ?text (tab del i m i t e d) (*.t xt )? as shown bel o w. then browse t o t h e fol d er where t h e export e d dri v e param e t e rs fi l e i s t o be saved, speci fy a fi l e nam e , and cl i c k save.
irmck203 application developer?s guide t h is docum ent is the pr oper t y of i n ter n ational rectifier and m a y not be copied or distr i but ed without expr essed consent. 23 c l i c k ok when t h e fol l o wi ng warni ng m e ssage appears: c l i c k yes when t h i s warni ng m e ssage appears: import drive parameters in servodesigner the final stage of drive param e ter conf iguration involves loading the drive pa ram e ter settings into a servodesigner dat a base and wri t i ng t h e regi st ers t o t h e ir m c k203. for i n form at i on about how t o use servodesi gner, refer t o t h e servodesi gner user?s gui d e. in part i c ul ar, sect i on 10. 3 of t h at docum ent descri bes t h e im port dri v e param e t e rs feature. the t e xt fi l e export e d from t h e excel workbook cont ai ns t w o sect i ons: param e t e rs and r e gi st ers. the parameters section the param e t e rs sect i on speci fi es m o t o r confi gurat i on param e t e rs, whi c h are saved i n t h e servodesi gner confi gurat i on file (.irc file). in serv o d esig n e r, th e settin g s can b e v i ewed and m odi fi ed by sel ect i ng m o t o r c onfi gurat i on from t h e preferen ces m e n u . w h en th e d r iv e p a ram e ters tex t file is im p o r ted in to serv o d esig n e r, th e m o to r co n f ig u r atio n param e ters in the im port text file always replace the current settings in th e servodesigner database. the registers section each o f th e en tries in th e reg i ster sectio n o f th e file id en tifie s a write register and a value to be st ored i n t h e regi st er. in a servodesigner database, there are several lo cations where each register value can be used: ? in the register definition, the value to w r ite is written to the corresponding ir mck203 register when the regi st er ent r y i s doubl e cl i c ked. ? also in th e reg i ster d e fin itio n , th e eeprom valu e to w r ite can b e sav e d to eeprom an d u s ed to in itialize t h e ir m c k203 regi st er on power up. ? in t h e funct i on defi ni t i ons sect i on, one or m o re func t i ons m a y wri t e t h e regi st er val u e t o t h e ir m c k203. (a funct i on i s set up t o perform a sequence of operat i ons aut o m a t i cal l y .) w h en t h e dri v e param e t e rs t e xt fi l e i s i m port e d i n t o servod esi gner, t h ere are several opt i ons for updat i ng any or al l of th ese reg i ster settin g s with th e v a lu e sp ecified in th e file. step 1. run servodesigner and open a database start servodesigner and select open from the file m e nu. servodesi gner confi gurat i on fi l e s have t h e fi l e ext e nsi on ?.i r c?. b r owse t o l o cat e a servodesi gner confi gurat i on fi l e and open i t . (to creat e a cust om confi gurat i on fi l e t o use with a specific project, it?s best to m a ke a copy of the exam ple file included with the release.)
irmck203 application developer?s guide t h is docum ent is the pr oper t y of i n ter n ational rectifier and m a y not be copied or distr i but ed without expr essed consent. 24 step 2. import drive parameters fro m th e file m e n u , select im p o r t, an d fro m th e im p o r t su b - m e n u , select driv e param e ters. bro w se to lo cate th e tex t fi l e t h at was export e d from excel and cl i c k open t o open i t . in t h e im port dri v e param e t e rs di al og, sel ect one of t h e t h ree avai l a bl e m odes and cl i c k ok. dependi ng on t h e sel ect ed m ode, servodesi gner m a y prom pt for confi r m a t i on before m odifying each regist er setting or group of settings. refer to the servodesigner user?s guide for m o re i n form at i on about t h e avai l a bl e m odes of operat i on. step 3. save the new settings the im port dri v e param e t e rs funct i on i n servodesi gner updat e s re gi st er val u es i n t h e dat a base t h at ?s current l y open. to save t h e new set t i ngs i n t h e confi gurat i on fi l e , sel ect save from t h e fi l e m e nu before exi t i ng servodesi gner. if this is not done, the updates will be lost, and the im port driv e param e ters function will need to be repeated next tim e t h e confi gurat i on fi l e i s opened. step 4. wri t e the setti ngs to the irmck203 the im port dri v e param e t e rs funct i on does not wri t e any val u es t o t h e ir m c k203; i t si m p l y updat e s t h e regi st er settings in the database. to transfer the register settings to the irmck203, it is necessary to either double click each wri t e regi st er i ndi vi dual l y (not recom m e nded) or execut e a funct i on t h at wri t e s t h e regi st ers aut o m a t i cal l y . the c onfi gure m o t o r funct i on i s pre-defi ned for t h i s purpose. to execut e t h e c onfi gure m o t o r funct i on, cl i c k t h e configure motor icon on the toolbar, or double click configure motor in the f unction definitions section of the tree vi ew. 3.1.2 evaluating drive perform ance the dri v e param e t e r t r ansl at i on as descri bed i n t h e previ ous sect i on i s t h e fi rst st ep of dri v e com m i ssi oni ng. it i s ex p ected th at th e u s er p a ram e ter en tries su ch as m o to r n a m e p l ate in fo rm atio n an d lo ad in ertia will h a v e at least 1 0 % error. this is typical due to the in accuracy in m o tor datasheet and load info rm ation. the drive perform ance can be furt her refi ned by goi ng t h rough dri v e di agnos t i c s as descri bed i n sect i on 3.1.3. for m o t o r cont rol purposes, t h e rot o r angl e i n form at i on i s req u i red to o p tim ally co n t ro l a perm an en t mag n e t ac m o t o r. in t h e ir m c k203, t h e cont rol i s perform ed wi t hout a shaft encoder (sensorl ess). the rot o r angl e i s estim ated u tilizin g m o to r p h a se (v, w ) cu rren t an d dc b u s v o ltag e feed b ack in fo rm atio n . in t h e ir m c k203 dri v e cont rol l e r, t h ere are 3 cont rol m odes (fi gure 11) for est i m at i on of t h e rot o r angl e for t h e ent i r e speed range including zero speed. during m o tor start-up pha se, the controller will go through these three control m odes i n sequence. these cont rol m odes are descri bed bel o w. sp e e d (3 ) c l o s e d -l o o p (2 ) o p e n -l o o p (1 ) p a r k in g 10% 100 % figure 11. driv e control modes 1 ) park in g ? th e in itial ro to r an g l e is id en tified b y fo rcin g dc cu rren t in to th e m o to r an d h e n ce fo rcin g th e m o tor shaft to park at a cer tain prescribed angle.
irmck203 application developer?s guide t h is docum ent is the pr oper t y of i n ter n ational rectifier and m a y not be copied or distr i but ed without expr essed consent. 25 2) open-l oop ? im m e di at el y aft e r parki ng st age, t h e rot o r angl e i s est i m at ed i n an open-l oop fashi on, whi c h u tilizes a sim p le m o to r-lo a d m ech an ical m o d e l to estim ate th e ro to r an g l e (estim ate lo ad ch aracteristics). if the m i sm atch between the external load characteristics and the intern al m o tor-load m odel is exceedingly larg e, start-u p p e rfo rm an ce will su ffer. 3) c l osed-l oop ? m o t o r speed i n creases duri ng st art - up; t h e m o t o r vol t a ge al so bui l d s up due t o t h e i n crease i n speed. useful inform ation for rotor angle estim ati on can be then be extract ed fro m th e m o to r v o ltag e (estim ated by using m o tor current and dc bus voltage). the drive w ill enter closed-loop control m ode as shown i n fi gure 11. 3.1.3 diagnostic mode functions di agnost i c m ode funct i ons are provi ded i n t h e servodesi gner t ool t o fi ne t une dri v e perform ance. it i s recom m e nded t o go t h rough di agnost i c m ode i n t h e proper orde r (parki ng di agnost i c t h en st art - up di agnost i c ). figure 12. parking diagnostic function parki n g di agnosti c w i t h t h e parki ng di agnost i c (shown i n fi gure 12), t h e opt i m al parki ng current (parki) and t h e parki ng t i m e durat i on (parktm ) can be readily determ ined. in addition, current cont rol l e r and current feedb ack can also be verified. w h en t h e parki ng di agnost i c funct i on i s execut e d, t h e dri v e i s forced t o st ay i n parki ng st at e for fi ve seconds, fol l o wed by a st op. the di agnost i c can be st opped any t i m e by execut i ng t h e st op m o t o r funct i on. the charact eri s t i c of parki ng depends on t h e am ount of dc current i n ject i on. it i s possi bl e t o veri fy current cont rol by observi ng t h e act ual current fl owi ng t h rough t h e m o t o r wi ndi ngs usi ng current sensi ng i n st rum e nt at i on (current probe). the am ount of parki ng current i n ject ed t o t h e m o t o r i s cont rol l e d by param e t e r parki as shown i n fi gure 12. the ful l scal e of parki i s 255 di gi t a l count s, whi c h represent s 86.7% rat e d m o t o r current (i n peak am ps). duri ng m o t o r parki ng, dc cu rrent i s i n ject ed (by i nvert er) i n t o w - phase and v-phase o f th e m o to r; th e cu rren t in u-p h a se is reg u l ated to zero . fo r in stan ce, if m o to r rated cu rren t is 2 . 7 a rm s, a v a lu e o f 77 digital counts in parki will produce 1 am p dc current in w - phase (- 1 am p) and v-phase (+ 1am p ). in practice, it is m u ch m o re than suffi cient to park a m o tor with rated m o tor current. if an exceedingly large value of parki is used, the m o tor shaft will hunt during parking. th is will increase the tim e for th e rotor shaft to settle and hence increase parking tim e. system s w ith a higher inertia to friction ratio w ill tend to hunt m o re. therefore, it is recom m e nded t o st art wi t h a l o wer val u e (say 4% parki = 12). the user can experience the effect of us i ng di fferent parki val u es. it m a y be not i ced t h at t h e parki ng charact eri s t i c s will also depend on the initial rotor angle (when drive is o ff). therefore, the shaft should be rotated (m anually, while the drive is off) to a different position before each parking evaluation. it is recom m e nd to use the highest possi bl e val u e (not t o cause excessi ve m o t o r hunt i ng) of parki such t h at t h e durat i on of parki ng can be m i ni m i zed. on ce th e o p tim al p a rk in g cu rren t (park i) is d e term in ed , p l ease n o t e th e tim e req u i red fo r th e m o to r sh aft to settle
irmck203 application developer?s guide t h is docum ent is the pr oper t y of i n ter n ational rectifier and m a y not be copied or distr i but ed without expr essed consent. 26 duri ng parki ng. thi s t i m e durat i on i s t h e opt i m al parki ng t i m e and shoul d be convert ed t o di gi t a l dri v e uni t s and ent e red i n t o regi st er parktm . the ful l scal e of parktm i s 255, whi c h represent s 4 seconds. after the parking diagnostic has been accom p lished, please en ter these two param e ters (parki and parktm ) into the sensorl e ss c t rl st art - up subfunct i on i n si de t h e c onfi gure m o t o r funct i on, as shown i n fi gure 13. note: to resum e norm a l m ode operat i on (out of di agnost i c ), t h e c onfi gure m o t o r funct i on m u st be execut e d agai n. figure 13. enter optimal parking parameters start-up di agnosti c thi s di agnost i c m ode i s provi ded t o fi ne t une open- l oop st art - up perform ance. duri ng open-l oop st art - up, t h e ir m c k203 cont rol ic est i m at es t h e rot o r angl e based on a si m p l e m o t o r l o ad m odel , whi c h uses onl y one confi gurabl e param e t e r (ktorque). the user param e t e r t r an slator (excel spreadsheet) al so g e n e rates th is p a ram e ter based on user i nput l o ad i n ert i a . use t h i s val u e as a st art i ng poi nt for fi ne t uni ng. the goal of t h i s st art - up di agnost i c i s t o fi ne t une t h i s param e t e r (ktorque) fo r opt i m al open-l oop dri v e cont rol perform ance. if a correct value of ktorque is used the drive w ill produce the highest torque per am pere ratio during open-loop start-up. the d r iv e m a y fail to start if ex cessiv e erro r is p r esen t in kto r q u e g a in . w h en the start-up diagnostic function is executed, the driv e will enter parking m ode follo wed by open-loop start-up. the drive will coast to a stop as soon as open-loop is accom p lished (determ i ned when m o tor frequency exceeds the level prescribed by write register w e thr). if an optim al value of ktorque is used , the drive will accelerate the m o t o r t o a hi gher speed si nce m a xi m u m t o rque per am pere i s achi e ved.
irmck203 application developer?s guide t h is docum ent is the pr oper t y of i n ter n ational rectifier and m a y not be copied or distr i but ed without expr essed consent. 27 figure 14. start-up diagnostic function users can observe m o t o r shaft m ovem e nt duri ng t h e st art - up di agnost i c t o det e rm i n e an opt i m al val u e of ktorque. as m e ntioned earlier, when the start-up diagnostic is in itiated, the drive will enter parking m ode for 4 seconds; thereafter open-loop start up will be initiate d. there will be shaft m ovem e nt due to parking of the m o tor during the initial 4 seconds. it is im portant to observe the shaft m ovem e nt only in the open-loop st artup period. an optim al ktorque value will generate higher st arting torque and hence increased m o tor shaft rotation during open-loop durat i on. if m easu r em en t in stru m e n t atio n (o scillo sco p e an d v o ltag e p r o b e ) is av ailab l e, it can b e u s ed to o b s erv e th e m o to r b ack em f t o det e rm i n e t h e opt i m al ktorque val u e. the m o t o r back em f i s proport i onal t o m o t o r speed. b y observi ng t h e m o t o r l i n e-l i n e vol t a ge at t h e end of t h e open-l oop peri od (i ndi cat ed by a m o m e nt ary hi gh pul se on d/ a convert er channel 4), i t i s possi bl e t o det e rm i n e an opt i m um val u e of ktorque. figure 15 and figure 16 illustrate two exam ple runs of the st art-up diagnostic with two di fferent values of ktorque bei ng used. as can be seen i n t h ese fi gures, aft e r open-l oop t e rm i n at es, t h e speed of t h e m o t o r coast s down. it i s apparent t h at t h e ktorque val u e used i n fi gure 16 provi de s hi gher vol t a ge and frequency ; hence t h e m o t o r speed i s al so hi gher. coast st opping op e n -l oo p mode motor li ne voltage da c 4 output figure 15. open-loop start (ktorque = 400)
irmck203 application developer?s guide t h is docum ent is the pr oper t y of i n ter n ational rectifier and m a y not be copied or distr i but ed without expr essed consent. 28 coast s t opping op e n -l oo p mode motor li ne voltage da c 4 output figure 16. open-loop start-up (ktorque = 520) aft e r t h e opt i m al val u e for ktorque has been det e rm i n ed, pl ease ent e r t h e val u e i n t o t h e sensorl e ss c t rl open-l oop subfunct i on i n si de t h e c onfi gure m o t o r funct i on as shown i n fi gure 17. resume normal operation after completing the diagnostic tests described in this section, the configure motor function must be executed i n o r d e r t o r e s u m e n o r m a l d r i v e m o d e . figure 17. enter optimal ktorque parameter 3.1.4 miscellaneous functions m i scel l a neous funct i ons provi ded i n t h e servodes i gner t ool are descri bed i n t h i s sect i on. phase loss detection thi s funct i on provi des det ect i on (duri ng st art - up) of a l oose wi re (u, v, w) bet w een dri v e and m o t o r.
irmck203 application developer?s guide this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 29 during motor parking (first stage of motor startup), a certain amount of dc current is injected into the motor windings for the purpose of initialization of rotor position. if motor feedback currents do not match the expected dc injection current level, a phase loss fault (phslossflt) is triggered. this fault can be disabled via bit 4 (phslosfltdisable field) of the mtrctrlbits write register. start-up retrial this function provides start-up retrials upon a start-up failure. start-up failure may occur if the motor shaft is jammed or motor starting torque cannot overcome shaft friction during startup. motor starting torque can be controlled by motor starting current limit (startlim) as shown in figure 18. the scaling of startlim is 4095 = rated motor current. the write registers written on execution of the startup retria l function are described below. the function is shown in figure 19. numretries ? this parameter determines the number of start- up retries. a value of zero will disable startup retry. the maximum number of retries is 15. flxthrl - the low flux threshold level for determining a successful startup (scaling: 129 = 100% flux). please do not modify this parameter without consulting a motor drive fae. flxthrh - the upper flux threshold le vel for determining a successful star tup (scaling: 64 = 100% flux). please do not modify this parameter without consulting a motor drive fae.
irmck203 application developer?s guide t h is docum ent is the pr oper t y of i n ter n ational rectifier and m a y not be copied or distr i but ed without expr essed consent. 30 startup current figure 18. configuring the startup current figure 19. start-up retrial function parkir et - duri ng m o t o r st art - up, dc current i s i n ject ed t o t h e m o t o r for m a xi m i zat i on of st art up t o rque per am pere rat i ng. users are abl e t o use a hi gher l e vel of dc current i n ject i on (parkir e t scal i ng 255 = m o t o r r a t e d am p * 0.866) after two or m o re restarts. this is done to increase the chance of a successful start-up.
irmck203 application developer?s guide t h is docum ent is the pr oper t y of i n ter n ational rectifier and m a y not be copied or distr i but ed without expr essed consent. 31 parktm r e t - duri ng m o t o r st art - up, dc current i s i n ject ed t o t h e m o t o r for m a xi m i zat i on of st art up t o rque per am pere rat i ng. parktm cont rol s t h e durat i on of dc current i n ject i on. however, users are abl e t o use a l onger durat i on aft e r t w o or m o re rest art s by set t i ng t h i s param e t e r (parktm r et scal i ng 255 = 4 secs.). thi s i s done t o i n crease t h e chance of a successful start-up. retrytm - th is p a ram e ter p r o v i d e s th e ad j u stm e n t to th e sam p lin g in stan t fo r d e term in atio n o f start failu re. th e sam p l i ng i n st ant st art s when c l osed_loop = 1. scal i ng 1 count = 1.966 m s ec. pl ease do not m odi fy t h i s param e t e r without consulting a m o tor drive fae. 3.2 standalone operation and register initialization via serial eeprom thi s sect i on descri bes t h e regi st er-cont rol l e d confi gura t i on and operat i on for an exam ple system that uses the irmck203 system in standal one m ode, which requires no in itialization by a host m i cropro cessor. in standalone m ode, the irmck203 initializes the host write registers from an i 2 c serial eeprom at power up and receives control com m a nds from the external hardware user interface signals during m o tor operation. the system described in this exam pl e i s shown i n fi gure 20. host wri t e r egist er s host re ad regist e r s is o l a t o r s inte lli gent ig bt m odu le (ir 2 136 + ig bt) ir 2 1 7 5 cu r r en t se n s e m o tor control func t i ons ig b t g a te con t ro l (6 ) gat ekill i r 2 175 c u rre n t se n s e br ake ig b t br ake v-ifb w-i f b phase u phase v phase w 20m o h m shu n t resist ors irmc x 203 motion co n t ro l p r ocess o r sta r t/stop atm e l atc24c01 128 byt e serial ee prom sc l sd a es top flt clr fa ult nsync ex t e r n a l u s e r c o n t r o l i nt er f a c e a/ d clk dat a e x t e r nal u s e r s pee d r ef 0 t o 5 v di r pm motor figure 20. irmck203 standalone sy stem 3.2.1 register initialization via eeprom each t i m e t h e ir m c k203 powers up, i t checks for val i d eepr o m dat a by readi ng a si ngl e by t e from eepr o m address 0x5d, whi c h represent s t h e ir m c k203 regi st er m a p versi on code. if t h i s val u e m a t c hes t h e ir m c k203 internal register m a p version, th e irmck203 eeprom initialization sequencer reads 128 sequential bytes from the eepr o m and st ores t h em i n host wri t e regi st ers 0 - 0x7f. if t h e user set s t h e l o cat i on i n t h e eepr o m t h at corresponds t o t h e sy st em c onfi g regi st er group?s ext c t r l fi el d t o ?1?, m o tor operation can be controlled direc tly using the external user interface im m e diately after power-on host write reg i ster in itializatio n .
irmck203 application developer?s guide this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 32 3.2.2 starting and stopping the motor to start or stop the motor in standalone mode, the user si mply drives the start/stop signal. section 2.4.1 describes the required i/os for sta ndalone mode operation. 3.2.3 fault processing when the irmck203 detects a fault condition, it disables pwm and asserts the ?f ault? signal. in standalone mode, the user clears the fault condition using the ?fltclr? signal. fault processing is otherwise identical to that described section 2.6
irmck203 application developer?s guide this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 33 4 reference 4.1 register access a host computer controls the irmck203 using its slave-mode full-duplex spi port, a standard rs-232 port or a 8-bit parallel port for connection to a micropro cessor. all interfaces are always ac tive and can be used interchangeably, although not simultaneously. control/status registers are mappe d into a 128-byte address space. 4.1.1 host parallel access the irmck203 contains an address register that is updated with the host register address when hp_a = 1. after each subsequent data byte is either read or written, the internal address regist er is incremented. the diagram below shows that data bytes 0 to n would acce ss register locations initially specified by the address byte. the address bye with the hp_a signal can be asserted at any time. address byte hp_a = 1 data byte 0 hp_a = 0 ?????. hp_a = 0 data byte n hp_a = 0 host parallel data transfer format 4.1.2 spi register access when configured as an spi device read only and read/wr ite operations are performed using the following transfer format: command byte data byte 0 ?????. data byte n data transfer format bit position 7 6 5 4 3 2 1 0 read only register map starting address command byte format data transfers begin at the address specified in the command byte and pro ceed sequentially until the spi transfer completes. as in the host parallel a ccess, the internal address register is incremented after each spi byte is transferred. note that accesses are read/w rite unless the ?read only? bit is set. 4.1.3 rs-232 register access the irmck203 includes an rs-232 interface channel that provides a direct conn ection to the host pc. the software interface combines a basic "register map" control met hod with a simple communicati on protocol to accommodate potential communication errors.
irmck203 application developer?s guide this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 34 rs-232 register write access a register write operation consists of a command/address by te, byte count, register data and checksum. when the irmck203 receives the register data, it validates the ch ecksum, writes the register data, and transmits and acknowledgement to the host. command / address byte byte count 1-6 bytes of register data checksum register write operation command acknowledgement byte checksum register write acknowledgement bit position 7 6 5 4 3 2 1 0 1=read/ 0=write register map starting address command/address byte format bit position 7 6 5 4 3 2 1 0 1=error/ 0=ok register map starting address command acknowledgement byte format the following example shows a command sequence sent from the host to the irmck203 requesting a two-byte register write operation: 0x2f write operation beginning at offset 0x2f 0x02 byte count of register data is 2 0x00 data byte 1 0x04 data byte 2 0x35 checksum (sum of preceding bytes, overflow discarded) a good reply from the irmck203 would appear as follows: 0x2f write completed ok at offset 0x2f 0x2f checksum an error reply to the command would have the following format: 0xaf write at offset 0x2f completed in error 0xaf checksum
irmck203 application developer?s guide this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 35 rs-232 register read access a register read operation consists of a command/address byte, byte count and checksum. when the irmck203 receives the command, it validates the checksum and transmits the register data to the host. command / address byte byte count checksum register read operation command acknowledgement byte register data (byte count bytes) checksum register read acknowledgement (transfer ok) command acknowledgement byte checksum register read acknowledgement (error) the following example shows a command sequence sent from the host to the irmck203 requesting four bytes of read register data: 0xa0 read operation beginning at offset 0x20 (high-order bit selects read operation) 0x04 requested data byte count is 4 0xa4 checksum a good reply from the irmck203 might appear as follows: 0x20 read completed ok at offset 0x20 0x11 data byte 1 0x22 data byte 2 0x33 data byte 3 0x44 data byte 4 0xca checksum an error reply to the command would have the following format: 0xa0 read at offset 0x20 completed in error 0xa0 checksum rs-232 timeout the irmck203 receiver includes a timer th at automatically terminates transfer s from the host to the irmck203 after a period of 32 msec. rs-232 transfer examples the following example shows a normal exch ange executing a register write access.
irmck203 application developer?s guide t h is docum ent is the pr oper t y of i n ter n ational rectifier and m a y not be copied or distr i but ed without expr essed consent. 36 the exam ple below shows a norm a l register read access exchange. the fol l o wi ng exam pl e shows a regi st er wri t e request t h at i s repeat ed by t h e host due t o a negat i v e acknowl e dgem e nt from t h e ir m c k203. in the final exam ple, the host repeats a register read access request when it r eceives no response to its first attem p t.
irmck203 application developer?s guide t h is docum ent is the pr oper t y of i n ter n ational rectifier and m a y not be copied or distr i but ed without expr essed consent. 37
irmck203 application developer?s guide this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 38 4.2 write register definitions 4.2.1 pwmconfig register group (write registers) byte offset bit position 7 6 5 4 3 2 1 0 0xc gatekill sns (w) spare gate snsl (w) gate snsu (w) syncsns brakesns sd (w) spare 0xd pwmperiod (lsbs) (w) 0xe twophs pwm (w) twophs type (w) pwmconfig (w) pwmperiod (msbs) (w) 0xf pwmdeadtm (w) 0x44 modscl (lsbs) (w) 0x45 modscl (msbs) (w) 0x51 pwmguardband (w) pwmconfig write register map field name access (r/w) field description sd w shutdown control output to ir2137. brakesns w logic sense for brake signal out put to gate driver ic. 0 = active low, 1 = active high. syncsns w logic sense for pwm sync si gnal output to microprocessor. 0 = active low, 1 = active high. gatesnsu w upper igbt gate sense. 1 = active high gate control, 0 = active low gate control. gatesnsl w lower igbt gate sense. 1 = active high gate control, 0 = active low gate control. gatekillsns w gatekill signal sense. 1 = active high gatekill, 0 = active low gatekill. pwmperiod w pwm carrier period. actual pwm carrier period is 2 * (pwmperiod + 1) * (system clock period). pwmconfig w pwm configuration. 0 = asymmetrical center aligned pwm, 1 = symmetrical center aligned pwm. twophstype w used only for two-phase pwm modulation mode: 0 = type 1 2-phase pwm 1 = type 2 2-phase pwm twophspwm w selects pwm modulation mode: 0 = enable 3-phase space vector pwm modulation 1 = enable 2-phase space vector pwm modulation
irmck203 application developer?s guide this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 39 field name access (r/w) field description pwmdeadtm w gate drive dead time in units of system clock cycles (e.g., 30 ns with 33 mhz clock). modscl w space vector modulator scale fa ctor. this register, which depends on the pwm carrier frequency, should be set as follows: modscl = pwmperiod * sqrt(3) * 4096 / 2355 where pwmperiod is the value in the pwmconfig write register group?s pwmperiod register. pwmguardband w this parameter provides a guard band (scaling: 1 = 30nsec) such that pwm switching will not mi grate into the current feedback sampling instant (sync pulse region). this guard band is provided to improve feedback noise. the parameter only applies to the 3- phase space vector modulation scheme. please do not modify this parameter without consulting a motor drive fae. pwmconfig write register field definitions 4.2.2 currentfeedbackconfig regist er group (write registers) byte offset bit position 7 6 5 4 3 2 1 0 0x15 ifbkscl (lsb) (w) 0x16 ifbkscl (msb) (w) 0x7d offsetcaldelay (w) currentfeedbackconfig write register map field name access (r/w) field description ifbkscl w rotating frame iq component and id component current feedback scale factor. constant used to scale current measurements before they are used in the field orientation calculation. this is a 15-bit fixed- point signed number with 10 fractional bits that ranges from ?16 to + 16 + 1023 / 1024. ifboffsvoffse tcal delay w this parameter specifies the delay ti me (1 = 1 sec) to restart current offset measurement after a stop command is issued. only applies if leg shunt current feedback is selected.12-bit signed value for v phase current feedback offset. when the ifboffsenb bit in the systemcontrol write register group is "0" this value is automatically added to each current measurement in hardware. currentfeedbackconfig write register field definitions
irmck203 application developer?s guide this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 40 4.2.3 systemcontrol register group (write registers) byte offset bit position 7 6 5 4 3 2 1 0 0x17 spare hostestop startcmd rotation systemcontrol write register map field name access (r/w) field description rotation w direction of motor rotation: 0 = reverse motor rotation; 1 = forward motor rotation. startcmd w start/stop bit. setting this bi t to 1 issues a start command. setting this bit to 0 stops the motor. hostestop w emergency coast stop will take place when this bit is set to one. systemcontrol write register field definitions 4.2.4 torqueloopconfig register group (write registers) byte offset bit position 7 6 5 4 3 2 1 0 0x1a kpireg ? current loop proportional gain (lsbs) (w) 0x1b kpireg ? current loop proportional gain (msbs) (w) 0x1c kxireg ? current loop integral gain (lsbs) (w) 0x1d kxireg ? current loop integral gain (msbs) (w) 0x22 vqlim ? quadrature current output limit (lsbs) (w) 0x23 vqlim ? quadrature current output limit (msbs) (w) 0x26 vdlim ? direct current output limit (lsbs) (w) 0x27 vdlim ? direct current output limit (msbs) (w) torqueloopconfig write register map
irmck203 application developer?s guide this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 41 field name access (r/w) field description kpireg w 15-bit signed current loop pi controller proportional gain. scaled with 14 fractional bits for an effective range of 0 ? 1. kxireg w 15-bit signed current loop pi cont roller integral gain. scaled with 19 fractional bits for an effective range of 0 - .03125. vqlim w 16-bit quadrature current pi controller voltage output limit. vdlim w 16-bit direct current pi controller voltage output limit. torqueloopconfig write register field definitions 4.2.5 velocitycontrol regist er group (write registers) byte offset bit position 7 6 5 4 3 2 1 0 0x32 kpsreg ? velocity loop proportional gain (lsbs) (w) 0x33 kpsreg ? velocity loop proportional gain (msbs) (w) 0x34 kxsreg ? velocity loop integral gain (lsbs) (w) 0x35 kxsreg ? velocity loop integral gain (msbs) (w) 0x36 motorlim ? velocity loop output positive limit (lsbs) (w) 0x37 motorlim ? velocity loop output positive limit (msbs) (w) 0x38 regenlim ? ? velocity loop output negative limit (lsbs) 0x39 regenlim ? ? velocity loop output negative limit (msbs) 0x3a spdscl ? speed scale factor (lsbs) 0x3b spdscl ? speed scale factor (msbs) 0x3c targetspd ? setpoint/target speed (lsbs) 0x3d targetspd ? setpoint/target speed (msbs) 0x3e accelrate 0x3f decelrate 0x7a minspd
irmck203 application developer?s guide this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 42 byte offset bit position 7 6 5 4 3 2 1 0 0x18 startlim (lsbs) 0x19 startlim (msbs) velocitycontrol write register map field name access (r/w) field description kpsreg w 15-bit velocity loop proportional gain, in fixed point with 5 fractional bits. range = 0 - 512. kxsreg w 15-bit velocity loop integral gain, in fixed point with 13 fractional bits. range = 0 - 2. motorlim w motoring torque current limit (4095 = rated motor current).16-bit speed pi controller output positive limit. regenlim w regeneration torque current limit (4095 = rated motor current)16-bit speed pi controller output negativ e limit (2?s complement).. spdscl w motor speed scale factor. spd value (in the velocitystatus read register group) is maintained in speed units of spdscl * (encoder counts / velocity loop execution) or spdscl * (rate * encoder counts / pwm period). the user should set spdscl = (64 * 16384) * 60 * pwmfreq / (rate * max rpm * encoder counts/revolution), which will result in a spd value ranging 16384 corresponding to max rpm. targetspd w velocity loop speed setpoint in speed units, which are determined by the user via the spdscl register setting. accelrate w positive speedacceleration rate limit. decelrate w negative speeddeceleration rate limit. minspd w minimum speed protection. th is parameter sets the minimum reference speed. startlim w drive start-up current limit. (4095 = rated motor current). velocitycontrol write register field definitions 4.2.6 faultcontrol register group (write registers) byte offset bit position 7 6 5 4 3 2 1 0 0x42 spare fltclr dcbusm enb faultcontrol write register map
irmck203 application developer?s guide this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 43 field name access (r/w) field description dcbusmenb w dc bus monitor enable. 1 = monitor dc bus voltage and generate appropriate brake signal control and disable pwm output when voltage fault conditions occur. gatekillflt and ovrspdflt faults cannot be disabled. dc bus voltage thresholds are as follows: overvoltage ? 410v brake on ? 380v brake off ? 360v nominal ? 310v undervoltage off ? 140v undervoltage ? 120v fltclr w this bit clears all active fault c onditions. the user should monitor the faultstatus read register group to determine fault status and set this bit to ?1? to clear any faults that have occurred. a fault condition automatically clears the pwmenbw and focenbw bits in the systemcontrol write register group. no te that this bit also directly controls the output 2137 fltclr pi n. after clearing a fault, the user must explicitly set this bit to ?0? to re-enable fault processing. faultcontrol write register field definitions 4.2.7 systemconfig register group (write registers) byte offset bit position 7 6 5 4 3 2 1 0 0x50 extctrl adcifbenb ramp stop spare systemconfig write register map field name access (r/w) field description rampstop w selects the stopping mode: 0 - configure for coast stopping 1 - configure for ramp stopping adcifbenb w selects the current feedback mode: 0 - selects ir2175 current feedback 1 - selects leg-shunt current feedback extctrl w setting this bit to ?1? enables direct control of basic motor operation via the external user interface pi ns. when this bit is ?1?, the focenbw and pwmenbw bits in the systemcontrol write register group are ignored. systemconfig write register field definitions
irmck203 application developer?s guide this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 44 4.2.8 eepromcontrol regist ers (write registers) at power up, the write registers can be optionally initialized with values stored in eeprom. the eepromcontrol write register group and eepromstatus read register group are used to read and write these eeprom values. since the eeaddrw write register (which selects the eeprom offset to read or write) does not require initialization at power up, the location corresponding to that register in eeprom (at offset 0x5d) is used to store a register map version code. at power on, the ir mck203 initializes the write registers from eeprom only if the version code stored at this offset in eeprom matches its internal register map version code (which can be read from the regmapver field of the eepromstatus read register group). to enable write register initialization at power up, write the appropriate register map version code to eeprom at offset 0x5d. to disable write register initialization at power up, write a zer o (or any non-matching version code) to offset 0x5d of the eeprom. byte offset bit position 7 6 5 4 3 2 1 0 0x5c spare eewrite eeread eerst 0x5d eeaddrw / regmapverscode (w) 0x5e eedataw (w) eepromcontrol write register map field name access (r/w) field description eerst w self-clearing eeprom reset. writing a "1" to this bit resets the i2c eeprom interface. eeread w self-clearing i2c eeprom read. writing a "1" to this bit initiates an eeprom read from the byte located at eeprom address eeaddrw. after setting this bit the user should poll the eebusy bit in the eepromstatus read register group to determine when the read completes and then read the data from eedatar in the eepromstatus read register group. eewrite w self-clearing eeprom write. writing a "1" to this bit initiates an eeprom write from the data byte in eedataw to the eeprom address eeaddrw . eeaddrw w eeprom address register. contains the address for the next eeprom read or write operation. eedataw w eeprom data register. contains the data for the next eeprom write operation. eepromcontrol write register field definitions
irmck203 application developer?s guide this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 45 4.2.9 closedloopangleestimator r egisters (write registers) byte offset bit position 7 6 5 4 3 2 1 0 0x60 iscl (lsbs) (w) 0x61 iscl (msbs (w) 0x62 flxbinit (lsbs) (w) 0x63 flxbinit (msbs) (w) 0x6a pllkp (lsbs) (w) 0x6b spare pllkp (msbs (w) 0x6c pllki (lsbs) (w) 0x6d spare pllki (msbs (w) 0x6e voltscl (lsbs) (w) 0x6f voltscl (msbs (w) 0x70 rs (lsbs) (w) 0x71 rs (msbs (w) 0x72 ld (lsbs) (w) 0x73 ld (msbs (w) 0x74 atantau (lsbs) (w) 0x75 atantau (msbs (w) 0x76 flxtau (lsbs) (w) 0x77 spare flxtau (msbs) (w) closedloopangleestimator write register map
irmck203 application developer?s guide this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 46 field name access (r/w) field description iscl w current scaler for motor flux calculation. flxbinit w initialization value of beta flux at start. pllkp w flux phase lock loop proportional gain. pllki w flux phase lock loop integral gain. voltscl w voltage scaler for motor flux calculation. rs w motor per phase resistance including cable (@25c). ld w motor per phase inductance. atantau w rotor angle estimator phase compensation gain. flxtau w rotor angle estimator flux model time constant. closedloopangleestimator write register field definitions 4.2.10 openloopangleestimator regi sters (write registers) byte offset bit position 7 6 5 4 3 2 1 0 0x66 ktorque (lsbs) (w) 0x67 ktorque (msbs (w) 0x5f vfgain (w) openloopangleestimator write register map field name access (r/w) field description ktorque w motor mechanical model torque constant. vfgain w open-loop volts/hz flux gain. (for diagnostic use only). openloopangleestimator write register field definitions 4.2.11 startupangleest imator registers (write registers) byte offset bit position 7 6 5 4 3 2 1 0 0x64 parki (w) 0x65 spare zero spdflt disable use2xfrq scale phslosflt disable diagnosticctrl (w) 0x68 wethr (lsbs) (w)
irmck203 application developer?s guide this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 47 byte offset bit position 7 6 5 4 3 2 1 0 0x69 wethr (msbs (w) 0x78 parktm (w) startupangleestimator write register map field name access (r/w) field description parki w dc current injection level during motor parking (start-up mode). diagnosticctrl w 1 (0001) ? enable parking diagnostic 2 (0010) ? enable start-up diagnostic 5 (0101) ? enable current regulator diagnostic 9 (1001) ? enable volts hertz diagnostic phslosflt disable w enable/disable phase loss fault: 0 = enable phase loss fault; 1 = disable phase loss fault use2xfrqscale w selects speed scaling: 0 - norminal speed scale 1 - reduce speed feedback scaling by half please do not modify this parameter without consulting motor control faes zerospdflt disable w zero speed fault enable/disable: 0 - enbale zero speed fault 1 - disable zero speed fault wethr w frequency threshold level (switch over from open-loop to closed- loop mode). parktm w time duration of parking mode. 255 = 4 sec startupangleestimator write register field definitions 4.2.12 startupretrial regi sters (write registers) byte offset bit position 7 6 5 4 3 2 1 0 0x1e retrytm (lsbs) 0x1f retrytm (msbs) 0x79 parktmret 0x7b flxthrl 0x7c flxthrh
irmck203 application developer?s guide this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 48 byte offset bit position 7 6 5 4 3 2 1 0 0x7e numretries 0x7f parkiret startupretrial write register map field name access (r/w) field description retrytm w this parameter provides the adjus tment to the sampling instant for determination of start failure. the sampling instant starts when closed_loop = 1. scaling 1 count = 1.966 msec. please do not modify this parameter without consulting a motor drive fae. parktmret w during motor start-up, dc current is injected to the motor for maximization of startup torque per ampere rating. parktm controls the duration of dc current injection. however, users are able to use a longer duration after two or more re starts by setting this parameter (parktmret scaling 255 = 4 secs.). this is done to increase the chance of a successful start-up.start-up failure may be caused by increased shaft friction. after first start-up retry, the parking time can be increased to improve parking performance. flxthrl w the low flux threshold leve l for determining a successful startup (scaling: 129 = 100% flux). please do not modify this parameter without consulting a motor drive fae.the low flux threshold level for determining a successful startup. flxthrh w the upper flux threshold leve l for determining a successful startup (scaling: 64 = 100% flux). please do not modify this parameter without consulting a motor drive fae.the high flux threshold level for determining start-up failure. numretries w if start-up fails, the user can program start-up retrial. this parameter determines the number of start-up retr ies. a value of zero will disable startup retrial. the maximum number of retries is 15. parkiret w during motor start-up, dc current is injected to the motor for maximization of startup torque per ampere rating. users are able to use a higher level of dc current injection (parkiret scaling 255 = motor rated amp * 0.866) after two or more restarts. this is done to increase the chance of a successful start-up.start-up failure may be caused by increased shaft friction. after first start-up retry, the parking current can be increased to improve parking performance. startupretrial write register field definitions
irmck203 application developer?s guide this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 49 4.2.13 phaselossdetect registers (write registers) byte offset bit position 7 6 5 4 3 2 1 0 0x79 parktmret 0x28 adjpark1 0x29 adjpark2 0x2a retrytm phaselossdetect write register map field name access (r/w) field description adjpark1 w anticipated w-phase motor current gain scaler used during initial stage of phase loss detection. adjpark2 w anticipated w-phase motor current gain scaler used during final stage of phase loss detection. phslosthr w phase loss detecti on current error thershold. phaselossdetect write register field definitions 4.2.14 d/aconverter regist ers (write registers) byte offset bit position 7 6 5 4 3 2 1 0 0x4f dacsel d/aconverter write register map
irmck203 application developer?s guide this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 50 field name access (r/w) field description dacsel w selects d/a converte r diagnostic outputs 0 - 3. a value of 0 selects: data 0 = alpha fluxflux data 1 = electrical rotor angle data 2 = alpha voltagetorque current data 3 = closed loop/open loop status (0 = open, 1 = closed) a value of 1 selects: data 0 = alpha currentdc bus voltage data 1 = torque current feedbackalpha voltage data 2 = iq reftorque current reference data 3 = motor speed a value of 2 selects: data 0 = q-axis command voltage data 1 = d-axis command voltage data 2 = alpha current data 3 = beta current a value of 3 selects: data 0 = flux magnitude data 1 = current error at parking data 2 = parking diagnostic flag data 3 = w-phase current d/aconverter write register field definitions 4.2.15 factory test register (write register) byte offset bit position 7 6 5 4 3 2 1 0 0x58 test factory write register map field name access (r/w) field description test w reserved for factory use. data written to this register could be read from a read register at location 0x58. factory write register field definitions
irmck203 application developer?s guide this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 51 4.3 read register definitions 4.3.1 systemstatus regist er group (read registers) byte offset bit position 7 6 5 4 3 2 1 0 0x7 startstop fwdrev estop pwrid extctrlr foc enbr pwm enbr systemstatus read register map field name access (r/w) field description pwmenbr r pwm enable bit status. focenbr r foc enable bit status. extctrlr r reflects the status of the extc trl bit in the system configuration write register (address 0x50). pwrid r power id. 0 = 3 kw, 1 = 2 kw, 2 = 500 w. estop r user interface emergency stop signal (1 ? emergency stop) fwdrev r user interface ?fwd /revdir" digital input status. 1 - forward rotation request 0 - reverse rotation request startstop r user interface ?sta rt/stop" digital input status. 1 - start 0 - stop systemstatus read register field definitions 4.3.2 dcbusvoltage regist er group (read registers) byte offset bit position 7 6 5 4 3 2 1 0 0xa dcbusvolts (lsbs) 0xb spare brake dcbusvolts (msbs) dcbusvoltage read register map
irmck203 application developer?s guide this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 52 field name access (r/w) field description dcbusvolts r dc bus voltage. data range is 0 - 4095, which corresponds to a dc bus voltage between 0 and 500 volts. brake r brake signal status. 1 = brake signal active. dcbusvoltage read regi ster field definitions 4.3.3 focdiagnosticdata regi ster group (read registers) byte offset bit position 7 6 5 4 3 2 1 0 0xc rotatorangle (lsb) 0xd spare parking done start_ fail closed_ loop rotatorangle (msb) 0xe id ? synchronous frame direct current (lsbs) 0xf id ? synchronous frame direct current (msbs) 0x10 iq ? synchronous frame quadrature current (lsbs) 0x11 iq ? synchronous frame quadrature current (msbs) 0x12 iqref_c ? synchronous frame quadrature current command (lsb) 0x13 iqref_c ? synchronous frame quadrature current command (msb) 0x14 flx_alpha ? estimated motor flux (lsb) 0x15 flx_alpha ? estimated motor flux (msb) 0x16 i_alpha ? alpha frame current (lsb) 0x17 i_alpha ? alpha frame current (msb) 0x18 v_alpha ? alpha frame voltage (lsb) 0x19 v_alpha ? alpha frame voltage (msb) focdiagnosticdata read register map
irmck203 application developer?s guide this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 53 field name access (r/w) field description rotatoranlge r estimated rotor angle (electrical), which is used for synchronous frame to stationary frame transformation. the scaling is 4096 = 2pi. the range is 0 ? 4095. closed_loop r this is a drive control status flag which indicates that the drive has switched from open-loop to closed-loop operation. the switch over is done during drive start-up (initial speed ramping) start_fail r this is a drive control status flag i ndicating that the drive has failed to start due to various reasons (for in stance: shaft jam). the start-stop sequencer uses this bit and param eter numretry to determine whether a start-up retry should be activated. parking done r this is a status flag indicating that the drive has finished obtaining the initial rotor angle (parking) for motor startup. during drive start-up, the first start-up stage is parking stage. id, iq r synchronous or rotating frame dire ct and quadrature current values in 2?s complement representation. the full scale current values range from ?16384 to 16383. (scaling: 4095 = rated motor current) iqref_c r synchronous or rotating frame quadr ature current command values in 2?s complement representation. the full scale current values range from ?16384 to 16383. flx_alpha r estimated motor flux value. scaling is 5000 = rated motor flux. i_alpha r stationary frame current. scali ng is platform dependent (current shunt resistor). drive commissi oning tool (spreadsheet) provides the scaling of i_alpha (aibi scale). v_alpha r stationary frame alpha voltage. this voltage is constructed by dc bus voltage and modulation index in the stationary frame. the scaling is platform dependent. focdiagnosticdata read regi ster field definitions 4.3.4 faultstatus register group (read registers) the fault status register records fault conditions that occur during drive operation. when any of these fault conditions occur, the pwm output is automatically disabled. the user should monitor this register continuously for fault conditions. a fault condition can be cleared by writing a ?1? to the faultclr bit in the faultcontrol write register group. (this does not automatically re-enable pwm output.) byte offset bit position 7 6 5 4 3 2 1 0 0x1e phsloss flt retryflt zerospd flt exectm flt ovrspdflt ovflt lvflt gatekillflt faultstatus read register map
irmck203 application developer?s guide this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 54 field name access (r/w) field description gatekillflt r filtered and latched version of ir2137 fault output. lvflt r dc bus low voltage fault. this fault occurs if the dc bus drops below 120v. ovflt r dc bus overvoltage fault. this fault occurs if the dc bus voltage exceeds 410v. ovrspdflt r over speed fault. this fault occu rs whenever the motor reaches the positive or negative limits. the user should use the scale factor in the spdscl field of the velocityc ontrol write register group to scale the motor speed so that it falls between -16384 and +16383 with these limits as the over speed condition. exectmflt r execution time fault. zerospdflt r zero speed fault. w hen speed is less than minspd/2 (half minimum speed) for a continuous period of 2 4 seconds, the zero speed fault will be set. retryflt r start-up retry fault. after a certain number (determined by parameter numretries) of start-up failures, this fault will be set. phslossflt r phase loss fault. drive to motor phase connection may be loose. faultstatus read regist er field definitions 4.3.5 velocitystatus regi ster group (read registers) byte offset bit position 7 6 5 4 3 2 1 0 0x26 spd (lsbs) 0x27 spd (msbs) velocitystatus read register map field name access (r/w) field description spd r current motor speed in speed units. (see the description of spdscl in the velocitycontrol write register group.) velocitystatus read register field definitions
irmck203 application developer?s guide this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 55 4.3.6 currentfeedbackoffset regi ster group (read registers) byte offset bit position 7 6 5 4 3 2 1 0 0x30 ifbvoffs (lsbs) (r) 0x31 ifbwoffs (lsbs) (r) ifbvoffs (msbs) (r) 0x32 ifbwoffs (msbs) (r) currentfeedbackoffset read register map field name access (r/w) field description ifbvoffs, ifbwoffs r current feedback offset values from t he last ifb offset calculation. these values are automatically applied to each current feedback measurement value whenever the ifboffsenb bit in the systemcontrol write register group is set. currentfeedbackoffset read register field definitions 4.3.7 eepromstatus regi sters (read registers) byte offset bit position 7 6 5 4 3 2 1 0 0x38 spare eebusy 0x39 eddatar (r) 0x3a eeaddrr (r) eepromstatus read register map field name access (r/w) field description eebusy r i2c eeprom interface busy bit. the user should wait for this bit to clear before initiating eeprom read or write operations. eedatar r eeprom data register. contains the data from the last eeprom read operation. note that writing to the eerst field in the eepromcontrol write register gr oup invalidates this register.
irmck203 application developer?s guide this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 56 field name access (r/w) field description eeaddrr r eeprom address read register shows the value stored in eeprom at the offset of the eeaddrw writ e register (0x5d). since this address in the eeprom contains the bpirmck203 register map version, the user can read this fi eld to determine whether or not the write registers were initialized at power on. eepromstatus read register field definitions 4.3.8 focdiagnosticdatasupplement r egister group (read registers) byte offset bit position 7 6 5 4 3 2 1 0 0x3c elecangr (lsbs) (r) 0x3d spare elecangr (msbs) (r) 0x3e spdref (lsbs) (r) 0x3f spdref (msbs) (r) 0x40 spderr (lsbs) (r) 0x41 spderr (msbs) (r) 0x42 iqrefr (lsbs) (r) 0x43 iqrefr (msbs) (r) focdiagnosticdatasupplement read register map field name access (r/w) field description elecangr r electrical angle. spdref r speed pi controller reference input. spderr r speed pi controller error. iqrefr r speed pi controller output. focdiagnosticdatasupplement read register field definitions
irmck203 application developer?s guide this document is the property of international rectifier and may not be copied or distribut ed without expressed consent. 57 4.3.9 productidentification r egisters (read registers) byte offset bit position 7 6 5 4 3 2 1 0 0x7c productid (r) 0x7d regmapverid (r) 0x7e revcodeid (lsbs) (r) 0x7f revcodeid (msbs) (r) productidentification read register map field name access (r/w) field description productid r product identification code. regmapverid r current register map version code. revcodeid r irmck203 revision code. revi sion code format is ?xx.xx?, where each ?x? is a 4-bit hexadecimal number. productidentification read re gister field definitions 4.3.10 factory register (read register) byte offset bit position 7 6 5 4 3 2 1 0 0x58 test (r) factory read register map field name access (r/w) field description test r data value resulting from a wr ite to write register 0x58. used for factory use only. factory read register field definitions
irmck203 application developer?s guide t h is docum ent is the pr oper t y of i n ter n ational rectifier and m a y not be copied or distr i but ed without expr essed consent. 58 appendix a space v e ctor pwm module the space vector pw m generation m odule accepts m odulation index com m a nds and generate s the appropriate gate drive waveform s for each pw m cycle. this section de scribes the operation and c onfiguration of the svpw m m odul e. svpwm basic theory and t ransfer characteristics a t h ree-phase 2-l e vel i nvert er wi t h dc l i nk confi gurat i on can have ei ght possi bl e swi t c hi ng st at es, whi c h generat e s output voltage of the inverter. each inverter switching state generates a volta ge space vector (v1 to v6 active vectors, v7 and v8 zero voltage vectors) in th e space vector plane (figure 21). the m a gnitude of each active vector (v1 to v6) i s 2/ 3 vdc (dc bus vol t a ge). the space vector pw m (svpw m ) m odule inputs m odulati on index com m a nds (u_alpha and u_beta) which are ort hogonal si gnal s (al pha and b e t a ) as shown i n fi gure 21. the gai n charact eri s t i c of t h e svpw m m odul e i s gi ven i n fi gure 22. the vert i cal axi s of fi gure 22 represent s t h e norm a l i zed peak m o t o r phase vol t a ge (v/ v dc) and t h e hori z ont al axi s represent s t h e norm a l i zed m odul at i on i ndex (m ). w h ere : 4 10 * _ * ? = ) _ _ ( 2 2 beta u alpha u + = (-32768 <= u_al pha, u_b e t a <= 32767) : input scal i ng fact or (0 t o 32767 range) scl mod _ the i nvert er fundam e nt al l i n e-t o -l i n e r m s out put vol t a ge (vl i n e) can be approxi m a t e d (l i n ear range) by t h e fol l o wi ng equat i on: 25 2 / 6 / * _ * vdc scl mod umag vline = where dc bus vol t a ge (vdc) i s i n vol t s v_alpha v_beta v1 v2 v3 v4 v5 v6 2 zero vectors v7, v8 sector 1 sector 2 sector 3 sector 4 sector 5 sector 6 v u-phase figure 21. space vector diagram
irmck203 application developer?s guide t h is docum ent is the pr oper t y of i n ter n ational rectifier and m a y not be copied or distr i but ed without expr essed consent. 59 sv pwm g a in 0 0. 1 0. 2 0. 3 0. 4 0. 5 0. 6 0. 7 0 1000 2000 3000 4000 5000 6000 7000 m v/ v d c figure 22. transfer characteristics the m a xi m u m achi e vabl e m odul at i on (um a g_l) i n t h e l i n ear operat i ng range i s gi ven by : scl mod l umag _ / 3 * 2 _ 25 & over modulation occurs when m odulation um ag > um ag_l. this corresponds to the condition where the voltage vector in figure 23 increases bey ond the hexagon boundary. under such ci rcum stance, the space vector pw m algorithm will rescale the m a gnitude of the voltage vector to f it within the hexagon lim it. the m a gnitude of the vol t a ge vect or i s rest ri ct ed wi t h i n t h e hexagon; however, t h e phase angl e ( ! ) is always preserved. the transfer gain (fi gure 22) of t h e pw m m odul at or reduces and becom e s non-l i n ear i n t h e over m odul at i on regi on. v1 v2 v3 v4 v5 v6 sector 1 sector 2 sector 3 sector 4 sector 5 sector 6 u-ph ase requ ested v o l tag e v ector gen e rated v o l tag e v ector figure 23. voltage vector rescaling
irmck203 application developer?s guide t h is docum ent is the pr oper t y of i n ter n ational rectifier and m a y not be copied or distr i but ed without expr essed consent. 60 pwm operation referring to figure 24, upon receiving the m odulation index com m a nds (u_a lpha and u_beta) the sub-m odule svpw m _ tm st art s i t s cal cul a t i ons at t h e ri si ng edge of t h e pwm l oad si gnal . the svpw m _ tm m odul e i m pl em ent s an algorithm that selects (based on sect or determ ination) the active space vector s (v1 to v6) being used and calculates the appropriate tim e duration (w.r.t. one pw m cycle) for each active vector. the appropr iated zero vectors are also bei ng sel ect ed. the svpw m _ tm m odul e consum es 11 cl ock cy cl es t y pi cal l y and 35 cl ock cy cl es (worst case tr) i n over m odulation cases. at the falling e dge of nsync, a new set of space vector tim es and vectors are readily avai l a bl e for act ual pw m generat i on (phaseu, phasev, phas ew ) by sub m odul e pwm g enerat i on. it i s cruci a l t o t r i gger pwm l oad at l east 35 cl ock cy cl es pri o r t o t h e fal l i ng edge of nsync si gnal ; ot herwi s e new m odul at i on co m m a n d s will n o t b e im p l em en ted at th e earliest pw m cycle. figure 24 (3-phase m odulation) and fi gure 25 (2-phase m odulation) illustrate s the pw m waveform s for a voltage vector locates in sector i of th e space vector plane (figure 21). the gating pattern outputs (pw m uh ? pw mw l) in clu d e d ead tim e in sertio n (d escrib e in later sectio n ) . nsync pwmload phaseu phasev phasew pwmuh pwmul pwmvh pwmvl pwmwh pwmwl tr td tpwm figure 24. 3-phase space vector pwm nsync pwmload phaseu phasev phasew pwmuh pwmul pwmvh pwmvl pwmwh pwmwl tr td tpwm figure 25. 2-phase (6-step pwm) space vector pwm
irmck203 application developer?s guide t h is docum ent is the pr oper t y of i n ter n ational rectifier and m a y not be copied or distr i but ed without expr essed consent. 61 pwm carrier period input vari abl e pwm c val cont rol s t h e durat i on of a pw m cy cl e. it shoul d be popul at ed by t h e sy st em cl ock frequency (c l k ) and pwm frequency (pwm freq) sel ect i on. the vari abl e shoul d be cal cul a t e d as: 1 ) * 2 /( ? = the input resolution of the space vector pw m m odulator signals u_alpha and u_beta is 16-bit signed integer. however, t h e act ual pw m resol u t i on (pwm c v al ) i s l i m i t e d by t h e sy st em cl ock frequency . deadtime insertion logic deadt i m e i s i n sert ed at t h e out put of t h e pw m generat i on m odul e. the resol u t i on i s 1 cl ock cy cl e, or 30 nsec at a 33.3 m h z cl ock and i s t h e sam e as t hose of t h e vol t a ge com m a nd regi st ers and t h e pw m carri er frequency regi st er. the deadt i m e i n sert i on l ogi c chops off t h e hi gh si de com m a nded vol t * seconds by t h e am ount of deadt i m e and adds t h e sam e am ount of vol t * seconds t o t h e l o w si de si gnal . thus, i t el i m i n at es t h e com p l e t e hi gh si de t u rn on pul se i f t h e com m a nded vol t * seconds i s l e ss t h an t h e program m e d deadt i m e. phaseu pwmuh pwmul deadtime deadtime figure 26. deadtime insertion the deadt i m e i n sert i on l ogi c i n sert s t h e program m e d deadt i m e bet w een t w o hi gh and l o w si de of t h e gat e si gnal s wi t h i n a phase. the deadt i m e regi st er i s al so doubl e buffered t o al l o w ?on t h e fl y ? deadt i m e change and cont rol whi l e pw m lo g i c is in activ e. symmetrical and asymmetrical mode operation there are t w o m odes of operat i on avai l a bl e for pw m wavefo rm generat i on, nam e l y t h e c e nt er al i gned sy m m e t r i cal pw m (fi gure 24) and t h e c e nt er al i gned asy m m e t r i cal pw m (fi gure 27). the vol t - sec can be changed every hal f a pw m cycle (tpwm ) since pwm l oad occurs every half a pw m cy cl e (com pare fi gure 24 and fi gure 27). w i t h sy m m e t r i cal pw m m ode, t h e i nvert er vol t a ge c onfi g = 0), t h e i nvert er vol t a ge can be changed at t w o t i m es t h e rat e of th e switch i n g freq u e n c y. th is will p r o v i d e an in crease in v o ltag e co n t ro l b a n d w id th , h o w ev er, at th e ex p e n s e o f increased current harm onics. the m ode of operat i on i s sel ect ed usi ng t h e pwm c onfi g fi el d of t h e pwm c onfi g wri t e regi st er group (descri b ed i n sect i on 4.2.1). to sel ect c e nt er al i gned asy m m e t r i cal pw m , set t h e pwm c onfi g fi el d t o ?0?. to sel ect c e nt er alig n e d sym m e trical pw m, set th e field to ?1 ?.
irmck203 application developer?s guide t h is docum ent is the pr oper t y of i n ter n ational rectifier and m a y not be copied or distr i but ed without expr essed consent. 62 nsync pwmload phaseu phasev phasew pwmuh pwmul pwmvh pwmvl pwmwh pwmwl tr td tpwm figure 27. asy mmetrical pwm mode three-phase and t w o-phase modulation three-phase and two-phase space vector pw m m odulation options are provided for the irmcx203. the volt-sec generat e d by t h e t w o pw m st rat e gi es are i d ent i cal ; howev er wi t h 2-phase m odul at i on t h e swi t c hi ng l o sses can be reduced si gni fi cant l y , especi al l y when hi gh swi t c hi ng frequency (>10khz) i s em pl oy ed. fi gure 28 shows t h e swi t c hi ng pat t e rn for one pw m cy cl e when t h e vol t a ge vect or i s i n si de sect or 1. p h ase u p h ase v p h ase w 3-ph ase m odu l a t i o n p h ase u p h ase v p h ase w 2-ph ase m odu l a t i o n v1 v2 v3 v4 v5 v6 2 ze ro v e c t or s v 7 , v 8 se cto r 1 se cto r 2 se cto r 3 se cto r 4 se cto r 5 se cto r 6 v u - phase figure 28. three-phase and tw o-phase modulation the fi el d twophspwm of t h e pwm c onfi g wri t e regi st er group (descri b ed i n sect i on 4.2.1) provi des sel ect i on of t h ree- phase or two-phase m odulation. the default setting is th ree-phase m odulation. succe ssful operation of two-phase m odulation in the entire speed operating range will depend on hardware configura tion. if the gate driver em ploys a bootstrap power supply strategy , m i soperation will occur at low m o tor f undam e ntal frequencies (< 2hz) under two- phase m odul at i on cont rol . there are t w o t y pes of t w o-phase m odul at i on schem e s provi ded. the fi el d twophsty pe i n t h e pwm c onfi g wri t e register group is used to select the ty pe, as described in section 4.2.1. fi gure 29 illustrates the different types of
irmck203 application developer?s guide t h is docum ent is the pr oper t y of i n ter n ational rectifier and m a y not be copied or distr i but ed without expr essed consent. 63 space vector pw m strategies availabl e for the irmcx203 product. inverter pole voltage and m o tor current are di spl a y e d i n fi gure 29. (a) three-phase pw m (b) two-phase (ty p e 1) pw m (c) two-phase (t y p e 2) pw m figure 29. different ty pes of space vector pwm
irmck203 application developer?s guide t h is docum ent is the pr oper t y of i n ter n ational rectifier and m a y not be copied or distr i but ed without expr essed consent. 64 appendix b ir2175 current sensing two channels of current feedback interface logic are pr ovided in the irmcx20x system . each m odule m easures the i n com i ng vary i ng dut y peri od of t h e 130 khz carri er freque ncy si gnal at t h e ir 2175out put . m easurem ent i s perform ed for bot h carri er frequency peri od and on dut y peri od at t h e sam e t i m e usi ng fast count ers. c ount i ng frequency i s 133 mhz with a 33.3 mhz system clock. the ir 2175 are t h e uni que hi gh vol t a ge ic s capabl e of m easuri ng t h e m o t o r phase current t h rough an associ at ed shunt resi st or, whi c h can generat e 260m v vol t a ge range. the out put of t h e ir 2175 i s an open drai n wi t h a 130 khz fi xed carri er frequency where t h e dut y vari ance i s l i n earl y propor t i onal t o 260 m v i nput vol t a ge. the count i ng frequency i s 133.3 m h z when t h e sy st em cl ock cry s t a l frequency i s 33.3 m h z, whi c h y i el ds 10-bi t resol u t i on of t h e current m easurem ent dat a from t h e ir 2175. the offset m easurem ent is autom a tically added aft e r t h e 10-bi t current m easurem ent has been calculated. the offset val u e m u st be cal cul a t e d and suppl i e d by ext e rnal hardware or soft ware. the peri od m easurem ent of bot h t h e carri er frequency pe ri od and t h e dut y peri od of t h e ir 2175 out put si gnal are perform ed. for carrier frequency period m easurem ent, there is a 16-stage averaging filter to sm ooth out the 130 khz carrier period of the ir2175. the m u ltip ly/divide com putation follows after com p leting both period m easurem ents. di vi de com put at i on bet w een t h e carri er frequency peri od a nd t h e dut y peri od al l e vi at es t e m p erat ure dri f t of t h e i n com i ng dat a off t h e ir 2175, si nce vari at i on of t h ese peri ods uni form l y m oves i n sam e di rect i on as t e m p erat ure changes. the m easured and adjust ed dat a i s coherent l y updat e d t o t h e host di gi t a l sy st em such as a m i crocont rol l e r, dsp, or fpga. a bl ock di agram of t h e current m easurem ent bl ock i s shown i n fi gure 30. ph a s e v pe r i o d c ount er di g i t a l fil t er p h as e v carri er frequ enc y p e ri o d c ount er a b b a x k k o ir21 75 40 96 i r 217 5 out put f a l l i n g edg e to con tro l b l o c k p h as e v p e r i od coh e s i ve lat c h p h as e v carri er frequ enc y p e ri o d c ohes i v e l a t c h in t e rn a l pw m sy n c s i gnal fil t er figure 30. current feedback measurement block the current feedback m odul e requi res a fast er cl ock t o count t h e dut y peri od of t h e i n com i ng pul se wi dt h m odul at ed si gnal from t h e ir 2175. thi s cl ock rat e i s desi gned t o work wi t h a frequency bet w een 120 m h z and 133.3 m h z. fi gure 31 depi ct s a si m p l e t i m e chart of count i ng.
irmck203 application developer?s guide t h is docum ent is the pr oper t y of i n ter n ational rectifier and m a y not be copied or distr i but ed without expr essed consent. 65 the duty counter, shown as ?ta? in figure 31, captures/latche s the value at the falling edge of ir2175 and reset. then t h e count er wai t s for t h e next ri si ng edge t o st art count i ng up. the carri er frequency count er (?tb ?) capt u res/ l a t c hes the value at the rising edge of ir2175 and is im m e diately followed by re-counting at each ifb event. at each ifb event, a m u ltiply/d ivide operation is perform ed to cancel the te m p erature drift error of m easurem ent. the fo llo win g is th e b a sic m u ltip ly/d iv id e o p e ratio n : ) ( _ 4096 ) ( n tb filtered n ta c a l c ul at i on st art s i m m e di at el y aft e r t h e ri si ng edge of t h e ir 2175 si gnal as shown i n fi gure 31. thi s l ook-ahead calcu latio n is req u i red to m i n i m i ze th e laten c y o f d a ta av ailab ility o f th e calcu latio n resu lt.
irmck203 application developer?s guide t h is docum ent is the pr oper t y of i n ter n ational rectifier and m a y not be copied or distr i but ed without expr essed consent. 66 pha s e v or w per i od c oun te r pha s e v or w ca r r i er f r equ en c y per i od c oun te r i n c o m i ng s i g nal f r o m ir 21 75 13 0k hz ( i r 2 17 5) d u t y v a ri es as s ens i n g c u rr ent c han ges t a (n -1 ) t b (n -1 ) i f b ev en t a fte r d i g i ta l f i l t e r i f b ev en t af t e r d i git a l f i l t er tb ( n ) ta ( n ) 13 0k hz ( i r 2 17 5) i f b ev en t a fte r d i g i t a l fi lte r 1 6 sy sclk = c a lu cu la te t a (n - 1 )* 40 9 6 / f i l t ere d_tb(n-1 ) 1 6 sy sclk = c a lu cu la te ta ( n )*409 6 / f i l t ere d _tb(n) figure 31. current feedback calculation timing
irmck203 application developer?s guide t h is docum ent is the pr oper t y of i n ter n ational rectifier and m a y not be copied or distr i but ed without expr essed consent. 67 ir w o rld h e adq u arters: 233 k a nsa s st., el segu n do , ca lifo r nia 90245, tel: (310) 252- 7105 http://www.irf.com data and speci fi cati ons subj ect to change wi thout noti ce. sal es offi ces, agents and di str i butor s i n maj o r ci ti es thr oughout the wor l d.

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